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fix comments

This commit is contained in:
Ilia Sergachev 2019-10-06 10:47:28 +02:00
parent 960b25a541
commit 2f7bd97129
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/icap.py
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@ -31,12 +31,12 @@ class ICAP(Module, AutoCSR):
self.sync += icap_clk_counter.eq(icap_clk_counter + 1)
self.sync += self.cd_icap.clk.eq(icap_clk_counter[3])
# Resychronize send pulse to icap domain ---------------------------------------------------
# Resynchronize send pulse to icap domain ---------------------------------------------------
ps_send = PulseSynchronizer("sys", "icap")
self.submodules += ps_send
self.comb += [ps_send.i.eq(self.send.re)]
# Generate icap bitstream write sequenceenerate icap bitstream write sequence
# Generate icap bitstream write sequence
_csib = Signal(reset=1)
_i = Signal(32)
_addr = self.addr.storage << 13