mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
use new MiSoC UART with phase accumulators
this will allow to speed up MiLa reads
This commit is contained in:
Florent Kermarrec
parent
452a4a76f3
commit
2fb418a373
1 changed files with 111 additions and 114 deletions
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@ -6,116 +6,113 @@ from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import split, displacer, chooser
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from migen.genlib.misc import split, displacer, chooser
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from migen.bank.description import *
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from migen.bank.description import *
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from migen.bus import wishbone
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from migen.bus import wishbone
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from migen.flow.actor import Sink, Source
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def rx_layout():
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class UARTRX(Module):
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return [
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def __init__(self, pads, tuning_word):
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("stb", 1, DIR_M_TO_S),
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self.source = Source([("d", 8)])
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("dat", 8, DIR_M_TO_S)
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]
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def tx_layout():
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return [
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("dat", 8, DIR_M_TO_S)
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]
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class UART(Module):
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def __init__(self, pads, clk_freq, baud=115200):
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self.rx = Record(rx_layout())
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self.tx = Record(tx_layout())
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self.divisor = Signal(16, reset=int(clk_freq/baud/16))
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pads.tx.reset = 1
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###
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###
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enable16 = Signal()
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uart_clk_rxen = Signal()
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enable16_counter = Signal(16)
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phase_accumulator_rx = Signal(32)
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self.comb += enable16.eq(enable16_counter == 0)
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self.sync += [
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enable16_counter.eq(enable16_counter - 1),
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If(enable16,
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enable16_counter.eq(self.divisor - 1))
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]
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# TX
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tx_reg = Signal(8)
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tx_bitcount = Signal(4)
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tx_count16 = Signal(4)
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tx_done = self.tx.ack
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tx_busy = Signal()
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tx_stb_d = Signal()
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self.sync += [
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tx_stb_d.eq(self.tx.stb & ~tx_done),
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tx_done.eq(0),
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If(self.tx.stb & ~tx_stb_d,
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tx_reg.eq(self.tx.dat),
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tx_bitcount.eq(0),
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tx_count16.eq(1),
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tx_busy.eq(1),
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pads.tx.eq(0)
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).Elif(enable16 & tx_busy,
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tx_count16.eq(tx_count16 + 1),
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If(tx_count16 == 0,
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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pads.tx.eq(1)
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).Elif(tx_bitcount == 9,
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pads.tx.eq(1),
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tx_busy.eq(0),
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tx_done.eq(1)
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).Else(
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pads.tx.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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)
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)
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)
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]
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# RX
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rx = Signal()
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rx = Signal()
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self.specials += MultiReg(pads.rx, rx, "sys")
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self.specials += MultiReg(pads.rx, rx)
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rx_r = Signal()
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rx_r = Signal()
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rx_reg = Signal(8)
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rx_reg = Signal(8)
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rx_bitcount = Signal(4)
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rx_bitcount = Signal(4)
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rx_count16 = Signal(4)
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rx_busy = Signal()
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rx_busy = Signal()
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rx_done = self.rx.stb
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rx_done = self.source.stb
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rx_data = self.rx.dat
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rx_data = self.source.payload.d
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self.sync += [
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self.sync += [
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rx_done.eq(0),
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rx_done.eq(0),
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If(enable16,
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rx_r.eq(rx),
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rx_r.eq(rx),
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If(~rx_busy,
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If(~rx_busy,
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If(~rx & rx_r, # look for start bit
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If(~rx & rx_r, # look for start bit
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rx_busy.eq(1),
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rx_busy.eq(1),
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rx_bitcount.eq(0),
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rx_count16.eq(7),
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)
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rx_bitcount.eq(0)
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).Else(
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)
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If(uart_clk_rxen,
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).Else(
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rx_bitcount.eq(rx_bitcount + 1),
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rx_count16.eq(rx_count16 + 1),
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If(rx_bitcount == 0,
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If(rx_count16 == 0,
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If(rx, # verify start bit
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rx_bitcount.eq(rx_bitcount + 1),
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rx_busy.eq(0)
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If(rx_bitcount == 0,
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If(rx, # verify start bit
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rx_busy.eq(0)
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)
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).Elif(rx_bitcount == 9,
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rx_busy.eq(0),
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If(rx, # verify stop bit
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rx_data.eq(rx_reg),
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rx_done.eq(1)
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)
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).Else(
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rx_reg.eq(Cat(rx_reg[1:], rx))
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)
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)
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).Elif(rx_bitcount == 9,
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rx_busy.eq(0),
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If(rx, # verify stop bit
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rx_data.eq(rx_reg),
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rx_done.eq(1)
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)
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).Else(
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rx_reg.eq(Cat(rx_reg[1:], rx))
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)
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)
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)
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)
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)
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)
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]
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]
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self.sync += \
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If(rx_busy,
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(phase_accumulator_rx + tuning_word)
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).Else(
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31)
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)
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class UARTTX(Module):
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def __init__(self, pads, tuning_word):
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self.sink = Sink([("d", 8)])
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###
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uart_clk_txen = Signal()
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phase_accumulator_tx = Signal(32)
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pads.tx.reset = 1
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tx_reg = Signal(8)
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tx_bitcount = Signal(4)
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tx_busy = Signal()
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self.sync += [
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self.sink.ack.eq(0),
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If(self.sink.stb & ~tx_busy & ~self.sink.ack,
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tx_reg.eq(self.sink.payload.d),
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tx_bitcount.eq(0),
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tx_busy.eq(1),
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pads.tx.eq(0)
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).Elif(uart_clk_txen & tx_busy,
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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pads.tx.eq(1)
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).Elif(tx_bitcount == 9,
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pads.tx.eq(1),
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tx_busy.eq(0),
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self.sink.ack.eq(1),
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).Else(
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pads.tx.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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)
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)
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]
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self.sync += [
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If(tx_busy,
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Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word)
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).Else(
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Cat(phase_accumulator_tx, uart_clk_txen).eq(0)
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)
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]
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class UART(Module, AutoCSR):
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def __init__(self, pads, clk_freq, baud=115200):
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# Tuning word value
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self._tuning_word = CSRStorage(32, reset=int((baud/clk_freq)*2**32))
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tuning_word = self._tuning_word.storage
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###
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self.submodules.rx = UARTRX(pads, tuning_word)
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self.submodules.tx = UARTTX(pads, tuning_word)
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class Counter(Module):
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class Counter(Module):
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def __init__(self, width):
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def __init__(self, width):
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@ -141,7 +138,7 @@ class UARTMux(Module):
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self.shared_pads = UARTPads()
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self.shared_pads = UARTPads()
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self.bridge_pads = UARTPads()
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self.bridge_pads = UARTPads()
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###
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###
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# Route rx pad:
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# Route rx pad:
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# when sel==0, route it to shared rx and bridge rx
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# when sel==0, route it to shared rx and bridge rx
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# when sel==1, route it only to bridge rx
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# when sel==1, route it only to bridge rx
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@ -167,7 +164,7 @@ class UART2Wishbone(Module, AutoCSR):
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WRITE_CMD = 0x01
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WRITE_CMD = 0x01
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READ_CMD = 0x02
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READ_CMD = 0x02
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def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
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def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
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# Wishbone interface
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# Wishbone interface
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self.wishbone = wishbone.Interface()
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self.wishbone = wishbone.Interface()
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if share_uart:
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if share_uart:
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@ -194,34 +191,34 @@ class UART2Wishbone(Module, AutoCSR):
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###
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###
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cmd = Signal(8)
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cmd = Signal(8)
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fsm.act("WAIT_CMD",
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fsm.act("WAIT_CMD",
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If(uart.rx.stb,
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If(uart.rx.source.stb,
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If( (uart.rx.dat == self.WRITE_CMD) |
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If( (uart.rx.source.payload.d == self.WRITE_CMD) |
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(uart.rx.dat == self.READ_CMD),
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(uart.rx.source.payload.d == self.READ_CMD),
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NextState("RECEIVE_BURST_LENGTH")
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NextState("RECEIVE_BURST_LENGTH")
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),
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),
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word_cnt.clr.eq(1),
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word_cnt.clr.eq(1),
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burst_cnt.clr.eq(1)
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burst_cnt.clr.eq(1)
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)
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)
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)
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)
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self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.stb, cmd.eq(uart.rx.dat))
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self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.source.stb, cmd.eq(uart.rx.source.d))
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####
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####
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burst_length = Signal(8)
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burst_length = Signal(8)
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fsm.act("RECEIVE_BURST_LENGTH",
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fsm.act("RECEIVE_BURST_LENGTH",
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word_cnt.inc.eq(uart.rx.stb),
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word_cnt.inc.eq(uart.rx.source.stb),
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If(word_cnt.value == 1,
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If(word_cnt.value == 1,
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word_cnt.clr.eq(1),
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word_cnt.clr.eq(1),
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NextState("RECEIVE_ADDRESS")
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NextState("RECEIVE_ADDRESS")
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)
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)
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)
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)
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self.sync += \
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self.sync += \
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If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.stb, burst_length.eq(uart.rx.dat))
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If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.source.stb, burst_length.eq(uart.rx.source.d))
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####
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####
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address = Signal(32)
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address = Signal(32)
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fsm.act("RECEIVE_ADDRESS",
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fsm.act("RECEIVE_ADDRESS",
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word_cnt.inc.eq(uart.rx.stb),
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word_cnt.inc.eq(uart.rx.source.stb),
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If(word_cnt.value == 4,
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If(word_cnt.value == 4,
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word_cnt.clr.eq(1),
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word_cnt.clr.eq(1),
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If(cmd == self.WRITE_CMD,
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If(cmd == self.WRITE_CMD,
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NextState("RECEIVE_DATA")
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NextState("RECEIVE_DATA")
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@ -231,8 +228,8 @@ class UART2Wishbone(Module, AutoCSR):
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)
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)
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)
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)
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self.sync += \
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self.sync += \
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If(fsm.ongoing("RECEIVE_ADDRESS") & uart.rx.stb,
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If(fsm.ongoing("RECEIVE_ADDRESS") & uart.rx.source.stb,
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address.eq(Cat(uart.rx.dat, address[0:24]))
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address.eq(Cat(uart.rx.source.d, address[0:24]))
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)
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)
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###
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###
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@ -240,8 +237,8 @@ class UART2Wishbone(Module, AutoCSR):
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###
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###
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fsm.act("RECEIVE_DATA",
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fsm.act("RECEIVE_DATA",
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word_cnt.inc.eq(uart.rx.stb),
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word_cnt.inc.eq(uart.rx.source.stb),
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If(word_cnt.value == 4,
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If(word_cnt.value == 4,
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word_cnt.clr.eq(1),
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word_cnt.clr.eq(1),
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NextState("WRITE_DATA")
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NextState("WRITE_DATA")
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)
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)
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@ -279,8 +276,8 @@ class UART2Wishbone(Module, AutoCSR):
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)
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)
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fsm.act("SEND_DATA",
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fsm.act("SEND_DATA",
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word_cnt.inc.eq(uart.tx.ack),
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word_cnt.inc.eq(uart.tx.sink.ack),
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If(word_cnt.value == 4,
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If(word_cnt.value == 4,
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burst_cnt.inc.eq(1),
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burst_cnt.inc.eq(1),
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If(burst_cnt.value == (burst_length-1),
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If(burst_cnt.value == (burst_length-1),
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NextState("WAIT_CMD")
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NextState("WAIT_CMD")
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@ -288,14 +285,14 @@ class UART2Wishbone(Module, AutoCSR):
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NextState("READ_DATA")
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NextState("READ_DATA")
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)
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)
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),
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),
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uart.tx.stb.eq(1),
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uart.tx.sink.stb.eq(1),
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chooser(data, word_cnt.value, uart.tx.dat, n=4, reverse=True)
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chooser(data, word_cnt.value, uart.tx.sink.d, n=4, reverse=True)
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)
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)
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###
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###
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self.sync += \
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self.sync += \
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If(fsm.ongoing("RECEIVE_DATA") & uart.rx.stb,
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If(fsm.ongoing("RECEIVE_DATA") & uart.rx.source.stb,
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data.eq(Cat(uart.rx.dat, data[0:24]))
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data.eq(Cat(uart.rx.source.d, data[0:24]))
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).Elif(fsm.ongoing("READ_DATA") & self.wishbone.stb & self.wishbone.ack,
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).Elif(fsm.ongoing("READ_DATA") & self.wishbone.stb & self.wishbone.ack,
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data.eq(self.wishbone.dat_r)
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data.eq(self.wishbone.dat_r)
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)
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)
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