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fhdl: support inverted clock ports in instances

This commit is contained in:
Sebastien Bourdeauducq 2012-09-22 20:50:49 +02:00
parent 2e14569b5c
commit 2fc9cae88a
2 changed files with 4 additions and 1 deletions
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3
migen/fhdl/structure.py
View File

@ -274,9 +274,10 @@ class Instance:
self.value = value self.value = value
class _CR: class _CR:
def __init__(self, name_inst, domain="sys"): def __init__(self, name_inst, domain="sys", invert=False):
self.name_inst = name_inst self.name_inst = name_inst
self.domain = domain self.domain = domain
self.invert = invert
class ClockPort(_CR): class ClockPort(_CR):
pass pass
class ResetPort(_CR): class ResetPort(_CR):

2
migen/fhdl/verilog.py
View File

@ -210,6 +210,8 @@ def _printinstances(f, ns, clock_domains):
elif isinstance(p, Instance.ClockPort): elif isinstance(p, Instance.ClockPort):
name_inst = p.name_inst name_inst = p.name_inst
name_design = ns.get_name(clock_domains[p.domain].clk) name_design = ns.get_name(clock_domains[p.domain].clk)
if p.invert:
name_design = "~" + name_design
elif isinstance(p, Instance.ResetPort): elif isinstance(p, Instance.ResetPort):
name_inst = p.name_inst name_inst = p.name_inst
name_design = ns.get_name(clock_domains[p.domain].rst) name_design = ns.get_name(clock_domains[p.domain].rst)