s6ddrphy: improve genericity by adding wr_bitslip and dqs_ddr_alignment parameters bitslip parameter is renamed to rd_bitslip
This commit is contained in:
Florent Kermarrec
Sebastien Bourdeauducq
parent
e7c72a826c
commit
307fb41ca3
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@ -27,12 +27,11 @@ from migen.genlib.record import *
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from milkymist import lasmicon
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class S6DDRPHY(Module):
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def __init__(self, pads, memtype, nphases, cl, bitslip):
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def __init__(self, pads, memtype, nphases, cl, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
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if memtype not in ["DDR", "LPDDR", "DDR2"]:
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raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
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if cl != 3:
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raise NotImplementedError("S6DDRPHY only supports CAS LATENCY 3")
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a = flen(pads.a)
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ba = flen(pads.ba)
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d = flen(pads.dq)
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@ -118,7 +117,7 @@ class S6DDRPHY(Module):
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bitslip_inc = Signal()
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sd_sys += [
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If(bitslip_cnt == bitslip,
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If(bitslip_cnt == rd_bitslip,
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bitslip_inc.eq(0)
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).Else(
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bitslip_cnt.eq(bitslip_cnt+1),
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@ -148,7 +147,7 @@ class S6DDRPHY(Module):
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for i in range(d//8):
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# DQS output
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self.specials += Instance("ODDR2",
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Instance.Parameter("DDR_ALIGNMENT", "C1"),
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Instance.Parameter("DDR_ALIGNMENT", dqs_ddr_alignment),
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Instance.Parameter("INIT", 0),
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Instance.Parameter("SRTYPE", "ASYNC"),
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@ -166,7 +165,7 @@ class S6DDRPHY(Module):
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# DQS tristate cmd
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self.specials += Instance("ODDR2",
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Instance.Parameter("DDR_ALIGNMENT", "C1"),
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Instance.Parameter("DDR_ALIGNMENT", dqs_ddr_alignment),
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Instance.Parameter("INIT", 0),
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Instance.Parameter("SRTYPE", "ASYNC"),
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@ -218,18 +217,20 @@ class S6DDRPHY(Module):
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drive_dq = Signal()
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drive_dq_n = Signal()
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d_drive_dq = Signal()
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d_drive_dq_n = Signal()
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self.comb += [
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drive_dq_n.eq(~drive_dq),
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d_drive_dq_n.eq(~d_drive_dq)
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]
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drive_dq_n = [Signal() for i in range(2)]
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self.comb += drive_dq_n[0].eq(~drive_dq)
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sd_sys += drive_dq_n[1].eq(drive_dq_n[0])
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dq_t = Signal(d)
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dq_o = Signal(d)
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dq_i = Signal(d)
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dq_wrdata = []
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for i in range(2):
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for j in reversed(range(nphases)):
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dq_wrdata.append(d_dfi[i*nphases+j].wrdata[:d])
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dq_wrdata.append(d_dfi[i*nphases+j].wrdata[d:])
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for i in range(d):
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# Data serializer
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self.specials += Instance("OSERDES2",
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@ -247,15 +248,16 @@ class S6DDRPHY(Module):
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Instance.Input("RST", 0),
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Instance.Input("CLKDIV", sys_clk),
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Instance.Input("D1", d_dfi[1*nphases+0].wrdata[i]),
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Instance.Input("D2", d_dfi[1*nphases+1].wrdata[i+d]),
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Instance.Input("D3", d_dfi[1*nphases+1].wrdata[i]),
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Instance.Input("D4", d_dfi[0*nphases+0].wrdata[i+d]),
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Instance.Input("D1", dq_wrdata[wr_bitslip+3][i]),
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Instance.Input("D2", dq_wrdata[wr_bitslip+2][i]),
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Instance.Input("D3", dq_wrdata[wr_bitslip+1][i]),
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Instance.Input("D4", dq_wrdata[wr_bitslip+0][i]),
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Instance.Output("TQ", dq_t[i]),
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Instance.Input("T1", d_drive_dq_n),
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Instance.Input("T2", d_drive_dq_n),
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Instance.Input("T3", d_drive_dq_n),
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Instance.Input("T4", drive_dq_n),
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Instance.Input("T1", drive_dq_n[(wr_bitslip+3)//4]),
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Instance.Input("T2", drive_dq_n[(wr_bitslip+2)//4]),
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Instance.Input("T3", drive_dq_n[(wr_bitslip+1)//4]),
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Instance.Input("T4", drive_dq_n[(wr_bitslip+0)//4]),
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Instance.Input("TRAIN", 0),
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Instance.Input("TCE", 1),
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Instance.Input("SHIFTIN1", 0),
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@ -309,6 +311,12 @@ class S6DDRPHY(Module):
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Instance.InOut("IO", pads.dq[i])
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)
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dq_wrdata_mask = []
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for i in range(2):
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for j in reversed(range(nphases)):
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dq_wrdata_mask.append(d_dfi[i*nphases+j].wrdata_mask[:d//8])
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dq_wrdata_mask.append(d_dfi[i*nphases+j].wrdata_mask[d//8:])
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for i in range(d//8):
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# Mask serializer
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self.specials += Instance("OSERDES2",
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@ -326,10 +334,11 @@ class S6DDRPHY(Module):
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Instance.Input("RST", 0),
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Instance.Input("CLKDIV", sys_clk),
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Instance.Input("D1", d_dfi[1*nphases+0].wrdata_mask[i]),
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Instance.Input("D2", d_dfi[1*nphases+1].wrdata_mask[i+d//8]),
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Instance.Input("D3", d_dfi[1*nphases+1].wrdata_mask[i]),
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Instance.Input("D4", d_dfi[0*nphases+0].wrdata_mask[i+d//8]),
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Instance.Input("D1", dq_wrdata_mask[wr_bitslip+3][i]),
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Instance.Input("D2", dq_wrdata_mask[wr_bitslip+2][i]),
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Instance.Input("D3", dq_wrdata_mask[wr_bitslip+1][i]),
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Instance.Input("D4", dq_wrdata_mask[wr_bitslip+0][i]),
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Instance.Output("TQ"),
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Instance.Input("T1"),
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Instance.Input("T2"),
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@ -359,7 +368,6 @@ class S6DDRPHY(Module):
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# DQ/DQS/DM control
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#
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self.comb += drive_dq.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
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sd_sys += d_drive_dq.eq(drive_dq)
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d_dfi_wrdata_en = Signal()
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sd_sys += d_dfi_wrdata_en.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
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2
top.py
2
top.py
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@ -92,7 +92,7 @@ class SoC(Module):
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#
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# DFI
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#
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", nphases=2, cl=3, bitslip=0)
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", nphases=2, cl=3, rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
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self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
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self.ddrphy.phy_settings.dfi_d, self.ddrphy.phy_settings.nphases)
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self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
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