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Merge pull request #1535 from Icenowy/c906-extcsr 

cpu/openc906: set extended CSRs based on D1 configuration
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enjoy-digital 2022-12-12 11:23:47 +01:00 committed by GitHub
parent 78fbb64c18 83aa3c031b
commit 30d68ce152
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1 changed files with 14 additions and 5 deletions
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19
litex/soc/cores/cpu/openc906/crt0.S
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@ -56,12 +56,21 @@ crt_init:
la sp, _fstack la sp, _fstack
la t0, trap_entry la t0, trap_entry
csrw mtvec, t0 csrw mtvec, t0
li t0, 0x400000 # Invalidate L1I+L1D, Branch History Table, Branch Target Bufer
csrs 0x7c0, t0 // enable THEADISAEE li t0, 0x70013
csrw 0x7c2, t0
# Enable L1I+L1D, Return Stack, BHT, BTB
li t0, 0x73 li t0, 0x73
csrs 0x7c1, t0 // enable L1$ (I+D) + Branch Prediction + Return Stack csrs 0x7c1, t0
li t0, 0x504 # Enable Unaligned Access, User-mode cache operation, CLINT S-mode
csrs 0x7c5, t0 // enable L1$ prefetching # interrupts, PTE memory attributes and T-HEAD extension
li t0, 0x638000
csrs 0x7c0, t0
# Enable L1I+L1D prefetch, Loop enhancement
# Bypass L1 for write operations larger than 3 cache lines
# Prefetch 8 cache lines
li t0, 0x450c
csrs 0x7c5, t0
data_init: data_init:
la t0, _fdata la t0, _fdata