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cpu/cv32e40p: add copyright and improve indentation.

This commit is contained in:
Florent Kermarrec 2020-05-22 15:55:35 +02:00
parent b23702ecc4
commit 30f3517041
1 changed files with 129 additions and 129 deletions
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16
litex/soc/cores/cpu/cv32e40p/core.py
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@ -1,4 +1,5 @@
#!/usr/bin/env python3 # This file is Copyright (c) 2019 Antmicro <www.antmicro.com>
# License: BSD
import os import os
import re import re
@ -113,7 +114,7 @@ class Wishbone2OBI(Module):
self.comb += [ self.comb += [
obi.we.eq(wb.we), obi.we.eq(wb.we),
obi.be.eq(wb.sel), obi.be.eq(wb.sel),
obi.addr.eq(Cat(0, 0, wb.adr)), obi.addr.eq(Cat(Signal(2), wb.adr)),
obi.wdata.eq(wb.dat_w), obi.wdata.eq(wb.dat_w),
wb.dat_r.eq(obi.rdata), wb.dat_r.eq(obi.rdata),
] ]
@ -133,7 +134,7 @@ class Wishbone2APB(Module):
) )
self.comb += [ self.comb += [
apb.paddr.eq(Cat(0, 0, wb.adr)), apb.paddr.eq(Cat(Signal(2), wb.adr)),
apb.pwrite.eq(wb.we), apb.pwrite.eq(wb.we),
apb.psel.eq(1), apb.psel.eq(1),
apb.pwdata.eq(wb.dat_w), apb.pwdata.eq(wb.dat_w),
@ -195,6 +196,7 @@ class TraceDebugger(Module):
self.submodules.bus_conv = Wishbone2APB(self.bus, apb) self.submodules.bus_conv = Wishbone2APB(self.bus, apb)
self.trace_params = dict( self.trace_params = dict(
# clk / rst
i_clk_i = ClockSignal(), i_clk_i = ClockSignal(),
i_rst_ni = ~ResetSignal(), i_rst_ni = ~ResetSignal(),
i_test_mode_i = 0, i_test_mode_i = 0,
@ -237,6 +239,9 @@ class DebugModule(Module):
("tdo", 1), ("tdo", 1),
] ]
def __init__(self, pads=None): def __init__(self, pads=None):
if pads is None:
pads = Record(self.jtag_layout)
self.pads = pads
self.dmbus = wishbone.Interface() self.dmbus = wishbone.Interface()
self.sbbus = wishbone.Interface() self.sbbus = wishbone.Interface()
dmbus = Record(obi_layout) dmbus = Record(obi_layout)
@ -252,11 +257,6 @@ class DebugModule(Module):
tdo_o = Signal() tdo_o = Signal()
tdo_oe = Signal() tdo_oe = Signal()
if pads is None:
pads = Record(self.jtag_layout)
self.pads = pads
self.specials += Tristate(pads.tdo, tdo_o, tdo_oe, tdo_i) self.specials += Tristate(pads.tdo, tdo_o, tdo_oe, tdo_i)
self.dm_params = dict( self.dm_params = dict(