cpu/cv32e40p: add copyright and improve indentation.

litex/soc/cores/cpu/cv32e40p/core.py

@@ -1,4 +1,5 @@
-#!/usr/bin/env python3
+# This file is Copyright (c) 2019 Antmicro <www.antmicro.com>
+# License: BSD
 
 import os
 import re
@@ -113,7 +114,7 @@ class Wishbone2OBI(Module):
         self.comb += [
             obi.we.eq(wb.we),
             obi.be.eq(wb.sel),
-            obi.addr.eq(Cat(0, 0, wb.adr)),
+            obi.addr.eq(Cat(Signal(2), wb.adr)),
             obi.wdata.eq(wb.dat_w),
             wb.dat_r.eq(obi.rdata),
         ]
@@ -133,7 +134,7 @@ class Wishbone2APB(Module):
         )
 
         self.comb += [
-            apb.paddr.eq(Cat(0, 0, wb.adr)),
+            apb.paddr.eq(Cat(Signal(2), wb.adr)),
             apb.pwrite.eq(wb.we),
             apb.psel.eq(1),
             apb.pwdata.eq(wb.dat_w),
@@ -195,6 +196,7 @@ class TraceDebugger(Module):
         self.submodules.bus_conv = Wishbone2APB(self.bus, apb)
 
         self.trace_params = dict(
+            # clk / rst
             i_clk_i               = ClockSignal(),
             i_rst_ni              = ~ResetSignal(),
             i_test_mode_i         = 0,
@@ -237,6 +239,9 @@ class DebugModule(Module):
         ("tdo",  1),
     ]
     def __init__(self, pads=None):
+        if pads is None:
+            pads = Record(self.jtag_layout)
+        self.pads = pads
         self.dmbus = wishbone.Interface()
         self.sbbus = wishbone.Interface()
         dmbus = Record(obi_layout)
@@ -252,11 +257,6 @@ class DebugModule(Module):
         tdo_o  = Signal()
         tdo_oe = Signal()
 
-        if pads is None:
-            pads = Record(self.jtag_layout)
-
-        self.pads = pads
-
         self.specials += Tristate(pads.tdo, tdo_o, tdo_oe, tdo_i)
 
         self.dm_params = dict(