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soc/interconnect/stream/: add busy signal to PipelinedActor

This commit is contained in:
Florent Kermarrec 2017-01-10 02:12:30 +01:00
parent 5eef105328
commit 30f7dd69bd
1 changed files with 5 additions and 1 deletions
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6
litex/soc/interconnect/stream.py
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@ -390,19 +390,23 @@ class PipelinedActor(BinaryActor):
def __init__(self, latency): def __init__(self, latency):
self.latency = latency self.latency = latency
self.pipe_ce = Signal() self.pipe_ce = Signal()
self.busy = Signal()
BinaryActor.__init__(self, latency) BinaryActor.__init__(self, latency)
def build_binary_control(self, sink, source, latency): def build_binary_control(self, sink, source, latency):
busy = 0
valid = sink.valid valid = sink.valid
for i in range(latency): for i in range(latency):
valid_n = Signal() valid_n = Signal()
self.sync += If(self.pipe_ce, valid_n.eq(valid)) self.sync += If(self.pipe_ce, valid_n.eq(valid))
valid = valid_n valid = valid_n
busy = busy | valid
self.comb += [ self.comb += [
self.pipe_ce.eq(source.ready | ~valid), self.pipe_ce.eq(source.ready | ~valid),
sink.ready.eq(self.pipe_ce), sink.ready.eq(self.pipe_ce),
source.valid.eq(valid) source.valid.eq(valid),
self.busy.eq(busy)
] ]
last = sink.valid & sink.last last = sink.valid & sink.last
for i in range(latency): for i in range(latency):