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soc/integration: Allow 0x400 CSR paging 

It's a convenient way to get more CSR locations without changing
the whole address space layout (i.e. more space for CSR).

It still leaves 256 full 32b registers in each location which
I've never encountered a device even coming close to this, so
it should be fairly safe to do.

This doesn't change the default, just allow the user to select it.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2024-02-05 11:45:34 +01:00
parent a59b67e4ee
commit 3127e504d3
1 changed files with 1 additions and 1 deletions
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litex/soc/integration/soc.py
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@ -652,7 +652,7 @@ class SoCCSRHandler(SoCLocHandler):
supported_data_width = [8, 32] supported_data_width = [8, 32]
supported_address_width = [14+i for i in range(4)] supported_address_width = [14+i for i in range(4)]
supported_alignment = [32] supported_alignment = [32]
supported_paging = [0x800*2**i for i in range(4)] supported_paging = [0x400*2**i for i in range(5)]
supported_ordering = ["big", "little"] supported_ordering = ["big", "little"]
# Creation ------------------------------------------------------------------------------------- # Creation -------------------------------------------------------------------------------------