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examples/wb_intercon: update to new APIs
This commit is contained in:
Sebastien Bourdeauducq
parent
6a9b59786b
commit
3143608e0a
4 changed files with 109 additions and 109 deletions
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@ -1,10 +1,10 @@
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from migen.fhdl import verilog
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from migen.bus import wishbone
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m1 = wishbone.Master("m1")
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m2 = wishbone.Master("m2")
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s1 = wishbone.Slave("s1")
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s2 = wishbone.Slave("s2")
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m1 = wishbone.Master()
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m2 = wishbone.Master()
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s1 = wishbone.Slave()
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s2 = wishbone.Slave()
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wishbonecon0 = wishbone.InterconnectShared(
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[m1, m2],
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[(0, s1), (1, s2)],
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@ -26,7 +26,7 @@ module master #(
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output reg [31:0] dat_w,
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input [31:0] dat_r,
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output reg [31:0] adr,
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output reg [29:0] adr,
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output reg we,
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output reg [3:0] sel,
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output cyc,
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@ -66,7 +66,7 @@ always @(posedge sys_clk) begin
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active <= 1'b0;
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end else if(~active) begin
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if(($random % p) == 0) begin
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adr <= (($random % 5)<< (32-2)) + id;
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adr <= (($random % 5) << (30-2)) + id;
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sel <= sel + 1;
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active <= 1'b1;
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if(($random % 2) == 0) begin
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@ -24,7 +24,7 @@ module slave #(
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input [31:0] dat_w,
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output reg [31:0] dat_r,
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input [31:0] adr,
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input [29:0] adr,
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input we,
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input [3:0] sel,
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input cyc,
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@ -1,6 +1,6 @@
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/*
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* Milkymist SoC
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* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
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* Copyright (C) 2007, 2008, 2009, 2011, 2012 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -23,54 +23,54 @@ reg sys_clk;
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//------------------------------------------------------------------
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// Wishbone master wires
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//------------------------------------------------------------------
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wire [31:0] wishbone_m1_adr,
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wishbone_m2_adr;
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wire [29:0] m1_wishbone_adr,
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m2_wishbone_adr;
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wire [31:0] wishbone_m1_dat_r,
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wishbone_m1_dat_w,
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wishbone_m2_dat_r,
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wishbone_m2_dat_w;
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wire [31:0] m1_wishbone_dat_r,
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m1_wishbone_dat_w,
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m2_wishbone_dat_r,
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m2_wishbone_dat_w;
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wire [3:0] wishbone_m1_sel,
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wishbone_m2_sel;
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wire [3:0] m1_wishbone_sel,
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m2_wishbone_sel;
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wire wishbone_m1_we,
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wishbone_m2_we;
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wire m1_wishbone_we,
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m2_wishbone_we;
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wire wishbone_m1_cyc,
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wishbone_m2_cyc;
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wire m1_wishbone_cyc,
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m2_wishbone_cyc;
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wire wishbone_m1_stb,
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wishbone_m2_stb;
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wire m1_wishbone_stb,
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m2_wishbone_stb;
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wire wishbone_m1_ack,
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wishbone_m2_ack;
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wire m1_wishbone_ack,
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m2_wishbone_ack;
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//------------------------------------------------------------------
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// Wishbone slave wires
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//------------------------------------------------------------------
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wire [31:0] wishbone_s1_adr,
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wishbone_s2_adr;
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wire [29:0] s1_wishbone_adr,
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s2_wishbone_adr;
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wire [31:0] wishbone_s1_dat_r,
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wishbone_s1_dat_w,
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wishbone_s2_dat_r,
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wishbone_s2_dat_w;
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wire [31:0] s1_wishbone_dat_r,
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s1_wishbone_dat_w,
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s2_wishbone_dat_r,
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s2_wishbone_dat_w;
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wire [3:0] wishbone_s1_sel,
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wishbone_s2_sel;
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wire [3:0] s1_wishbone_sel,
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s2_wishbone_sel;
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wire wishbone_s1_we,
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wishbone_s2_we;
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wire s1_wishbone_we,
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s2_wishbone_we;
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wire wishbone_s1_cyc,
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wishbone_s2_cyc;
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wire s1_wishbone_cyc,
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s2_wishbone_cyc;
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wire wishbone_s1_stb,
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wishbone_s2_stb;
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wire s1_wishbone_stb,
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s2_wishbone_stb;
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wire wishbone_s1_ack,
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wishbone_s2_ack;
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wire s1_wishbone_ack,
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s2_wishbone_ack;
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//---------------------------------------------------------------------------
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// Wishbone switch
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@ -80,84 +80,84 @@ intercon dut(
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.sys_rst(sys_rst),
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// Master 0
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.wishbone_m1_dat_o(wishbone_m1_dat_w),
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.wishbone_m1_dat_i(wishbone_m1_dat_r),
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.wishbone_m1_adr_o(wishbone_m1_adr),
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.wishbone_m1_we_o(wishbone_m1_we),
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.wishbone_m1_sel_o(wishbone_m1_sel),
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.wishbone_m1_cyc_o(wishbone_m1_cyc),
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.wishbone_m1_stb_o(wishbone_m1_stb),
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.wishbone_m1_ack_i(wishbone_m1_ack),
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.m1_wishbone_dat_o(m1_wishbone_dat_w),
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.m1_wishbone_dat_i(m1_wishbone_dat_r),
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.m1_wishbone_adr_o(m1_wishbone_adr),
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.m1_wishbone_we_o(m1_wishbone_we),
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.m1_wishbone_sel_o(m1_wishbone_sel),
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.m1_wishbone_cyc_o(m1_wishbone_cyc),
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.m1_wishbone_stb_o(m1_wishbone_stb),
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.m1_wishbone_ack_i(m1_wishbone_ack),
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// Master 1
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.wishbone_m2_dat_o(wishbone_m2_dat_w),
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.wishbone_m2_dat_i(wishbone_m2_dat_r),
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.wishbone_m2_adr_o(wishbone_m2_adr),
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.wishbone_m2_we_o(wishbone_m2_we),
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.wishbone_m2_sel_o(wishbone_m2_sel),
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.wishbone_m2_cyc_o(wishbone_m2_cyc),
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.wishbone_m2_stb_o(wishbone_m2_stb),
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.wishbone_m2_ack_i(wishbone_m2_ack),
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.m2_wishbone_dat_o(m2_wishbone_dat_w),
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.m2_wishbone_dat_i(m2_wishbone_dat_r),
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.m2_wishbone_adr_o(m2_wishbone_adr),
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.m2_wishbone_we_o(m2_wishbone_we),
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.m2_wishbone_sel_o(m2_wishbone_sel),
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.m2_wishbone_cyc_o(m2_wishbone_cyc),
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.m2_wishbone_stb_o(m2_wishbone_stb),
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.m2_wishbone_ack_i(m2_wishbone_ack),
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// Slave 0
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.wishbone_s1_dat_o(wishbone_s1_dat_r),
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.wishbone_s1_dat_i(wishbone_s1_dat_w),
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.wishbone_s1_adr_i(wishbone_s1_adr),
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.wishbone_s1_sel_i(wishbone_s1_sel),
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.wishbone_s1_we_i(wishbone_s1_we),
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.wishbone_s1_cyc_i(wishbone_s1_cyc),
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.wishbone_s1_stb_i(wishbone_s1_stb),
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.wishbone_s1_ack_o(wishbone_s1_ack),
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.s1_wishbone_dat_o(s1_wishbone_dat_r),
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.s1_wishbone_dat_i(s1_wishbone_dat_w),
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.s1_wishbone_adr_i(s1_wishbone_adr),
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.s1_wishbone_sel_i(s1_wishbone_sel),
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.s1_wishbone_we_i(s1_wishbone_we),
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.s1_wishbone_cyc_i(s1_wishbone_cyc),
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.s1_wishbone_stb_i(s1_wishbone_stb),
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.s1_wishbone_ack_o(s1_wishbone_ack),
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// Slave 1
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.wishbone_s2_dat_o(wishbone_s2_dat_r),
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.wishbone_s2_dat_i(wishbone_s2_dat_w),
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.wishbone_s2_adr_i(wishbone_s2_adr),
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.wishbone_s2_sel_i(wishbone_s2_sel),
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.wishbone_s2_we_i(wishbone_s2_we),
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.wishbone_s2_cyc_i(wishbone_s2_cyc),
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.wishbone_s2_stb_i(wishbone_s2_stb),
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.wishbone_s2_ack_o(wishbone_s2_ack)
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.s2_wishbone_dat_o(s2_wishbone_dat_r),
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.s2_wishbone_dat_i(s2_wishbone_dat_w),
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.s2_wishbone_adr_i(s2_wishbone_adr),
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.s2_wishbone_sel_i(s2_wishbone_sel),
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.s2_wishbone_we_i(s2_wishbone_we),
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.s2_wishbone_cyc_i(s2_wishbone_cyc),
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.s2_wishbone_stb_i(s2_wishbone_stb),
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.s2_wishbone_ack_o(s2_wishbone_ack)
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);
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//---------------------------------------------------------------------------
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// Masters
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//---------------------------------------------------------------------------
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wire wishbone_m1_end;
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wire m1_wishbone_end;
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master #(
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.id(0)
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) m0 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_m1_dat_w),
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.dat_r(wishbone_m1_dat_r),
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.adr(wishbone_m1_adr),
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.we(wishbone_m1_we),
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.sel(wishbone_m1_sel),
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.cyc(wishbone_m1_cyc),
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.stb(wishbone_m1_stb),
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.ack(wishbone_m1_ack),
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.dat_w(m1_wishbone_dat_w),
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.dat_r(m1_wishbone_dat_r),
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.adr(m1_wishbone_adr),
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.we(m1_wishbone_we),
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.sel(m1_wishbone_sel),
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.cyc(m1_wishbone_cyc),
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.stb(m1_wishbone_stb),
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.ack(m1_wishbone_ack),
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.tend(wishbone_m1_end)
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.tend(m1_wishbone_end)
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);
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wire wishbone_m2_end;
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wire m2_wishbone_end;
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master #(
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.id(1)
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) m1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_m2_dat_w),
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.dat_r(wishbone_m2_dat_r),
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.adr(wishbone_m2_adr),
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.we(wishbone_m2_we),
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.sel(wishbone_m2_sel),
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.cyc(wishbone_m2_cyc),
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.stb(wishbone_m2_stb),
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.ack(wishbone_m2_ack),
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.dat_w(m2_wishbone_dat_w),
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.dat_r(m2_wishbone_dat_r),
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.adr(m2_wishbone_adr),
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.we(m2_wishbone_we),
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.sel(m2_wishbone_sel),
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.cyc(m2_wishbone_cyc),
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.stb(m2_wishbone_stb),
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.ack(m2_wishbone_ack),
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.tend(wishbone_m2_end)
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.tend(m2_wishbone_end)
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);
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//---------------------------------------------------------------------------
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@ -170,14 +170,14 @@ slave #(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_s1_dat_w),
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.dat_r(wishbone_s1_dat_r),
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.adr(wishbone_s1_adr),
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.we(wishbone_s1_we),
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.sel(wishbone_s1_sel),
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.cyc(wishbone_s1_cyc),
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.stb(wishbone_s1_stb),
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.ack(wishbone_s1_ack)
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.dat_w(s1_wishbone_dat_w),
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.dat_r(s1_wishbone_dat_r),
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.adr(s1_wishbone_adr),
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.we(s1_wishbone_we),
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.sel(s1_wishbone_sel),
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.cyc(s1_wishbone_cyc),
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.stb(s1_wishbone_stb),
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.ack(s1_wishbone_ack)
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);
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slave #(
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@ -186,20 +186,20 @@ slave #(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_s2_dat_w),
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.dat_r(wishbone_s2_dat_r),
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.adr(wishbone_s2_adr),
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.we(wishbone_s2_we),
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.sel(wishbone_s2_sel),
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.cyc(wishbone_s2_cyc),
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.stb(wishbone_s2_stb),
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.ack(wishbone_s2_ack)
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.dat_w(s2_wishbone_dat_w),
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.dat_r(s2_wishbone_dat_r),
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.adr(s2_wishbone_adr),
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.we(s2_wishbone_we),
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.sel(s2_wishbone_sel),
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.cyc(s2_wishbone_cyc),
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.stb(s2_wishbone_stb),
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.ack(s2_wishbone_ack)
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);
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initial sys_clk = 1'b0;
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always #5 sys_clk = ~sys_clk;
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wire all_end = wishbone_m1_end & wishbone_m2_end;
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wire all_end = m1_wishbone_end & m2_wishbone_end;
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always begin
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$dumpfile("intercon.vcd");
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