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soc: Add separators for SoC Main Components.

This commit is contained in:
Florent Kermarrec 2024-04-02 10:25:59 +02:00
parent 06083c7863
commit 31508ddfa4
1 changed files with 7 additions and 0 deletions
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7
litex/soc/integration/soc.py
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@ -1027,6 +1027,8 @@ class SoC(LiteXModule, SoCCoreCompat):
raise SoCError() raise SoCError()
# SoC Main Components -------------------------------------------------------------------------- # SoC Main Components --------------------------------------------------------------------------
# Add Controller -------------------------------------------------------------------------------
def add_controller(self, name="ctrl", **kwargs): def add_controller(self, name="ctrl", **kwargs):
self.check_if_exists(name) self.check_if_exists(name)
self.logger.info("Controller {} {}.".format( self.logger.info("Controller {} {}.".format(
@ -1034,6 +1036,7 @@ class SoC(LiteXModule, SoCCoreCompat):
colorer("added", color="green"))) colorer("added", color="green")))
self.add_module(name=name, module=SoCController(**kwargs)) self.add_module(name=name, module=SoCController(**kwargs))
# Add/Init RAM ---------------------------------------------------------------------------------
def add_ram(self, name, origin, size, contents=[], mode="rwx"): def add_ram(self, name, origin, size, contents=[], mode="rwx"):
ram_cls = { ram_cls = {
"wishbone": wishbone.SRAM, "wishbone": wishbone.SRAM,
@ -1097,12 +1100,14 @@ class SoC(LiteXModule, SoCCoreCompat):
colorer(f"0x{contents_size:x}"))) colorer(f"0x{contents_size:x}")))
ram.mem.depth = len(contents) ram.mem.depth = len(contents)
# Add/Init ROM ---------------------------------------------------------------------------------
def add_rom(self, name, origin, size, contents=[], mode="rx"): def add_rom(self, name, origin, size, contents=[], mode="rx"):
self.add_ram(name, origin, size, contents, mode=mode) self.add_ram(name, origin, size, contents, mode=mode)
def init_rom(self, name, contents=[], auto_size=True): def init_rom(self, name, contents=[], auto_size=True):
self.init_ram(name, contents, auto_size) self.init_ram(name, contents, auto_size)
# Add CSR Bridge -------------------------------------------------------------------------------
def add_csr_bridge(self, name="csr", origin=None, register=False): def add_csr_bridge(self, name="csr", origin=None, register=False):
csr_bridge_cls = { csr_bridge_cls = {
"wishbone": wishbone.Wishbone2CSR, "wishbone": wishbone.Wishbone2CSR,
@ -1141,6 +1146,7 @@ class SoC(LiteXModule, SoCCoreCompat):
self.add_config("CSR_DATA_WIDTH", self.csr.data_width) self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
self.add_config("CSR_ALIGNMENT", self.csr.alignment) self.add_config("CSR_ALIGNMENT", self.csr.alignment)
# Add CPU --------------------------------------------------------------------------------------
def add_cpu(self, name="vexriscv", variant="standard", reset_address=None, cfu=None): def add_cpu(self, name="vexriscv", variant="standard", reset_address=None, cfu=None):
from litex.soc.cores import cpu from litex.soc.cores import cpu
@ -1284,6 +1290,7 @@ class SoC(LiteXModule, SoCCoreCompat):
if hasattr(self.cpu, "nop"): if hasattr(self.cpu, "nop"):
self.add_config("CPU_NOP", self.cpu.nop) self.add_config("CPU_NOP", self.cpu.nop)
# Add Timer ------------------------------------------------------------------------------------
def add_timer(self, name="timer0"): def add_timer(self, name="timer0"):
from litex.soc.cores.timer import Timer from litex.soc.cores.timer import Timer
self.check_if_exists(name) self.check_if_exists(name)