generic: add crossbar and use it in mac/ip/udp
This commit is contained in:
Florent Kermarrec
parent
f0993ea422
commit
3187a93984
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@ -1,7 +1,8 @@
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from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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from liteeth.core.ip.crossbar import LiteEthIPV4Crossbar
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from liteeth.generic.crossbar import LiteEthCrossbar
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from liteeth.core.ip.common import *
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class LiteEthIPV4Depacketizer(LiteEthDepacketizer):
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def __init__(self):
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@ -19,6 +20,17 @@ class LiteEthIPV4Packetizer(LiteEthPacketizer):
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ipv4_header,
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ipv4_header_len)
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class LiteEthIPV4Crossbar(LiteEthCrossbar):
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def __init__(self):
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LiteEthCrossbar.__init__(self, LiteEthIPV4MasterPort, "protocol")
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def get_port(self, protocol):
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if protocol in self.users.keys():
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raise ValueError("Protocol {0:#x} already assigned".format(protocol))
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port = LiteEthIPV4UserPort(8)
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self.users[protocol] = port
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return port
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class LiteEthIPV4Checksum(Module):
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def __init__(self, words_per_clock_cycle=1, skip_checksum=False):
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self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog
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@ -1,33 +0,0 @@
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from collections import OrderedDict
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from liteeth.common import *
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from liteeth.generic.arbiter import Arbiter
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from liteeth.generic.dispatcher import Dispatcher
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from liteeth.core.ip.common import *
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class LiteEthIPV4Crossbar(Module):
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def __init__(self):
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self.users = OrderedDict()
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self.master = LiteEthIPV4MasterPort(8)
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def get_port(self, protocol):
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if protocol in self.users.keys():
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raise ValueError("Protocol {0:#x} already assigned".format(protocol))
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port = LiteEthIPV4UserPort(8)
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self.users[protocol] = port
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return port
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def do_finalize(self):
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# TX arbitrate
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sinks = [port.sink for port in self.users.values()]
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self.submodules.ip_arbiter = Arbiter(sinks, self.master.source)
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# RX dispatch
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sources = [port.source for port in self.users.values()]
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self.submodules.ip_dispatcher = Dispatcher(self.master.sink, sources, one_hot=True)
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cases = {}
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cases["default"] = self.ip_dispatcher.sel.eq(0)
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for i, (k, v) in enumerate(self.users.items()):
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cases[k] = self.ip_dispatcher.sel.eq(2**i)
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self.comb += \
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Case(self.master.sink.protocol, cases)
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@ -1,7 +1,8 @@
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from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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from liteeth.core.udp.crossbar import LiteEthUDPCrossbar
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from liteeth.generic.crossbar import LiteEthCrossbar
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from liteeth.core.udp.common import *
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class LiteEthUDPDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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@ -19,6 +20,33 @@ class LiteEthUDPPacketizer(LiteEthPacketizer):
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udp_header,
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udp_header_len)
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class LiteEthUDPCrossbar(LiteEthCrossbar):
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def __init__(self):
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LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port")
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def get_port(self, udp_port, dw=8):
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if udp_port in self.users.keys():
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raise ValueError("Port {0:#x} already assigned".format(udp_port))
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user_port = LiteEthUDPUserPort(dw)
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internal_port = LiteEthUDPUserPort(8)
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if dw != 8:
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converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8))
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self.submodules += converter
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self.comb += [
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Record.connect(user_port.sink, converter.sink),
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Record.connect(converter.source, internal_port.sink)
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]
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converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw))
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self.submodules += converter
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self.comb += [
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Record.connect(internal_port.source, converter.sink),
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Record.connect(converter.source, user_port.source)
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]
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self.users[udp_port] = internal_port
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else:
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self.users[udp_port] = user_port
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return user_port
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class LiteEthUDPTX(Module):
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def __init__(self, ip_address):
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self.sink = sink = Sink(eth_udp_user_description(8))
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@ -1,49 +0,0 @@
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from collections import OrderedDict
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from liteeth.common import *
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from liteeth.generic.arbiter import Arbiter
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from liteeth.generic.dispatcher import Dispatcher
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from liteeth.core.udp.common import *
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class LiteEthUDPCrossbar(Module):
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def __init__(self):
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self.users = OrderedDict()
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self.master = LiteEthUDPMasterPort(8)
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def get_port(self, udp_port, dw=8):
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if udp_port in self.users.keys():
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raise ValueError("Port {0:#x} already assigned".format(udp_port))
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user_port = LiteEthUDPUserPort(dw)
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internal_port = LiteEthUDPUserPort(8)
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if dw != 8:
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converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8))
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self.submodules += converter
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self.comb += [
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Record.connect(user_port.sink, converter.sink),
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Record.connect(converter.source, internal_port.sink)
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]
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converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw))
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self.submodules += converter
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self.comb += [
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Record.connect(internal_port.source, converter.sink),
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Record.connect(converter.source, user_port.source)
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]
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self.users[udp_port] = internal_port
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else:
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self.users[udp_port] = user_port
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return user_port
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def do_finalize(self):
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# TX arbitrate
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sinks = [port.sink for port in self.users.values()]
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self.submodules.udp_arbiter = Arbiter(sinks, self.master.source)
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# RX dispatch
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sources = [port.source for port in self.users.values()]
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self.submodules.udp_dispatcher = Dispatcher(self.master.sink, sources, one_hot=True)
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cases = {}
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cases["default"] = self.udp_dispatcher.sel.eq(0)
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for i, (k, v) in enumerate(self.users.items()):
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cases[k] = self.udp_dispatcher.sel.eq(2**i)
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self.comb += \
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Case(self.master.sink.dst_port, cases)
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@ -8,7 +8,7 @@ class Arbiter(Module):
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pass
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elif len(sources) == 1:
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self.grant = Signal()
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self.comb += Record.connect(sources[0], sink)
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self.comb += Record.connect(sources.pop(), sink)
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else:
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self.submodules.rr = RoundRobin(len(sources))
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self.grant = self.rr.grant
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@ -0,0 +1,30 @@
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from collections import OrderedDict
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from liteeth.common import *
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from liteeth.generic.arbiter import Arbiter
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from liteeth.generic.dispatcher import Dispatcher
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class LiteEthCrossbar(Module):
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def __init__(self, master_port, dispatch_param):
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self.users = OrderedDict()
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self.master = master_port(8)
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self.dispatch_param = dispatch_param
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# overload this in derived classes
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def get_port(self, *args, **kwargs):
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pass
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def do_finalize(self):
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# TX arbitrate
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sinks = [port.sink for port in self.users.values()]
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self.submodules.arbiter = Arbiter(sinks, self.master.source)
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# RX dispatch
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sources = [port.source for port in self.users.values()]
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self.submodules.dispatcher = Dispatcher(self.master.sink, sources, one_hot=True)
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cases = {}
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cases["default"] = self.dispatcher.sel.eq(0)
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for i, (k, v) in enumerate(self.users.items()):
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cases[k] = self.dispatcher.sel.eq(2**i)
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self.comb += \
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Case(getattr(self.master.sink, self.dispatch_param), cases)
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@ -6,7 +6,7 @@ class Dispatcher(Module):
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if len(sinks) == 0:
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self.sel = Signal()
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elif len(sinks) == 1:
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self.comb += Record.connect(source, sinks[0])
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self.comb += Record.connect(source, sinks.pop())
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self.sel = Signal()
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else:
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if one_hot:
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@ -1,9 +1,10 @@
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from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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from liteeth.generic.crossbar import LiteEthCrossbar
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from liteeth.mac.core import LiteEthMACCore
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from liteeth.mac.frontend.common import *
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from liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface
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from liteeth.mac.frontend.crossbar import LiteEthMACCrossbar
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class LiteEthMACDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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@ -21,6 +22,17 @@ class LiteEthMACPacketizer(LiteEthPacketizer):
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mac_header,
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mac_header_len)
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class LiteEthMACCrossbar(LiteEthCrossbar):
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def __init__(self):
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LiteEthCrossbar.__init__(self, LiteEthMACMasterPort, "ethernet_type")
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def get_port(self, ethernet_type):
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port = LiteEthMACUserPort(8)
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if ethernet_type in self.users.keys():
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raise ValueError("Ethernet type {0:#x} already assigned".format(ethernet_type))
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self.users[ethernet_type] = port
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return port
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class LiteEthMAC(Module, AutoCSR):
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def __init__(self, phy, dw, interface="crossbar", endianness="big",
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with_hw_preamble_crc=True):
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@ -1,33 +0,0 @@
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from collections import OrderedDict
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from liteeth.common import *
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from liteeth.generic.arbiter import Arbiter
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from liteeth.generic.dispatcher import Dispatcher
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from liteeth.mac.frontend.common import *
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class LiteEthMACCrossbar(Module):
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def __init__(self):
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self.users = OrderedDict()
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self.master = LiteEthMACMasterPort(8)
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def get_port(self, ethernet_type):
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port = LiteEthMACUserPort(8)
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if ethernet_type in self.users.keys():
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raise ValueError("Ethernet type {0:#x} already assigned".format(ethernet_type))
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self.users[ethernet_type] = port
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return port
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def do_finalize(self):
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# TX arbitrate
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sinks = [port.sink for port in self.users.values()]
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self.submodules.mac_arbiter = Arbiter(sinks, self.master.source)
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# RX dispatch
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sources = [port.source for port in self.users.values()]
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self.submodules.mac_dispatcher = Dispatcher(self.master.sink, sources, one_hot=True)
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cases = {}
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cases["default"] = self.mac_dispatcher.sel.eq(0)
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for i, (k, v) in enumerate(self.users.items()):
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cases[k] = self.mac_dispatcher.sel.eq(2**i)
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self.comb += \
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Case(self.master.sink.ethernet_type, cases)
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