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etherbone: wip

This commit is contained in:
Florent Kermarrec 2015-02-10 16:43:24 +01:00
parent 310040b43b
commit 31bdc48a57
3 changed files with 117 additions and 113 deletions
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120
liteeth/core/etherbone/__init__.py
View File

@ -1,29 +1,12 @@
from liteeth.common import * from liteeth.common import *
from liteeth.generic.depacketizer import LiteEthDepacketizer from liteeth.core.etherbone import common
from liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthEtherboneDepacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_udp_user_description(8),
eth_etherbone_description(8),
etherbone_header,
etherbone_header_len)
class LiteEthEtherbonePacketizer(LiteEthPacketizer):
def __init__(self):
LiteEthPacketizer.__init__(self,
eth_etherbone_description(8),
eth_udp_user_description(8),
etherbone_header,
etherbone_header_len)
class LiteEthEtherboneTX(Module): class LiteEthEtherboneTX(Module):
def __init__(self, udp_port): def __init__(self, udp_port):
self.sink = sink = Sink(eth_etherbone_user_description(8)) self.sink = sink = Sink(eth_etherbone_user_description(32))
self.source = source = Source(eth_udp_user_description(8)) self.source = source = Source(eth_udp_user_description(32))
### ###
self.submodules.packetizer = packetizer = LiteEthUDPPacketizer() self.submodules.packetizer = packetizer = LiteEthEtherbonePacketizer()
self.comb += [ self.comb += [
packetizer.sink.stb.eq(sink.stb), packetizer.sink.stb.eq(sink.stb),
packetizer.sink.sop.eq(sink.sop), packetizer.sink.sop.eq(sink.sop),
@ -72,8 +55,8 @@ class LiteEthEtherboneTX(Module):
class LiteEthEtherboneRX(Module): class LiteEthEtherboneRX(Module):
def __init__(self): def __init__(self):
self.sink = sink = Sink(eth_udp_user_description(8)) self.sink = sink = Sink(eth_udp_user_description(32))
self.source = source = Source(eth_etherbone_user_description(8)) self.source = source = Source(eth_etherbone_user_description(32))
### ###
self.submodules.depacketizer = depacketizer = LiteEtherboneDepacketizer() self.submodules.depacketizer = depacketizer = LiteEtherboneDepacketizer()
self.comb += Record.connect(sink, depacketizer.sink) self.comb += Record.connect(sink, depacketizer.sink)
@ -122,100 +105,11 @@ class LiteEthEtherboneRX(Module):
) )
) )
class LiteEthEtherboneWishboneMaster(Module):
def __init__(self):
self.sink = sink = Sink(eth_etherbone_user_description(8))
self.source = source = Source(eth_etherbone_description(8))
self.bus = bus = wishbone.Interface()
###
self.submodules.base_addr = base_addr = FlipFlop(32)
self.comb += self.base_addr.d.eq(self.sink.data)
self.submodules.counter = counter = Counter(32)
self.submodules.fifo = fifo = SyncFIFO([("data", 32)], 256)
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
sink.ack.eq(1),
counter.reset.eq(1),
If(sink.stb & sink.sop,
If(sink.wcount > 0,
self.base_addr.ce.eq(1),
NextState("WRITE_DATA")
).Elif(sink.rcount > 0,
self.base_addr.ce.eq(1),
NextState("READ_DATA")
)
)
)
fsm.act("WRITE_DATA",
bus.adr.eq(base_addr + self.counter.value),
bus.dat_w.eq(sink.data),
bus.sel.eq(0xf), # XXX?
bus.stb.eq(sink.stb),
bus.we.eq(1),
bus.cyc.eq(1),
If(bus.stb & bus.ack,
sink.ack.eq(1),
counter.ce.eq(1),
If(counter.value == sink.wcount-1,
If(sink.rcount > 0,
counter.reset.eq(1)
NextState("READ_DATA")
).Else(
NextState("TERMINATE")
)
)
)
)
fsm.act("CHECK_READ",
If(sink.rcount > 0,
If(sink.stb,
sink.ack.eq(1),
base_addr.ce.eq(1),
NextState("READ_DATA")
)
).Else(
NextState("IDLE")
)
)
fsm.act("READ_DATA",
bus.adr.eq(self.sink.data),
bus.sel.eq(0xf),
bus.stb.eq(1),
bus.we.eq(0),
bus.cyc.eq(1),
If(bus.stb & bus.ack,
sink.ack.eq(1),
counter.ce.eq(1),
fifo.sink.stb.eq(1),
fifo.sink.sop.eq(counter == 0),
fifo.sink.data.eq(bus.dat_r),
If(counter.value == sink.rcount-1,
fifo.sink.eop.eq(1),
NextState("PRESENT_DATA")
)
)
)
fsm.act("PRESENT_DATA",
source.stb.eq(fifo.stb),
source.sop.eq(fifo.sop),
source.eop.eq(fifo.eop),
fifo.ack.eq(source.ack),
source.length.eq(sink.rcount+1),
source.wcount.eq(sink.rcount),
source.rcount.eq(0),
If(source.stb & source.eop & source.ack,
NextState("IDLE")
)
)
class LiteEthEtherbone(Module): class LiteEthEtherbone(Module):
def __init__(self, udp, udp_port): def __init__(self, udp, udp_port):
self.submodules.tx = tx = LiteEthEtherboneTX(udp_port) self.submodules.tx = tx = LiteEthEtherboneTX(udp_port)
self.submodules.rx = rx = LiteEthEtherboneRX() self.submodules.rx = rx = LiteEthEtherboneRX()
udp_port = udp.crossbar.get_port(udp_port) udp_port = udp.crossbar.get_port(udp_port, dw=32)
self.comb += [ self.comb += [
Record.connect(tx.source, udp_port.sink), Record.connect(tx.source, udp_port.sink),
Record.connect(udp_port.source, rx.sink) Record.connect(udp_port.source, rx.sink)

19
liteeth/core/etherbone/common.py Normal file
View File

@ -0,0 +1,19 @@
from liteeth.common import *
from liteeth.generic.depacketizer import LiteEthDepacketizer
from liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthEtherboneDepacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_udp_user_description(32),
eth_etherbone_description(32),
etherbone_header,
etherbone_header_len)
class LiteEthEtherbonePacketizer(LiteEthPacketizer):
def __init__(self):
LiteEthPacketizer.__init__(self,
eth_etherbone_description(32),
eth_udp_user_description(32),
etherbone_header,
etherbone_header_len)

91
liteeth/core/etherbone/master.py Normal file
View File

@ -0,0 +1,91 @@
from liteeth.common import *
from liteeth.core.etherbone import common
class LiteEthEtherboneWishboneMaster(Module):
def __init__(self):
self.sink = sink = Sink(eth_etherbone_user_description(32))
self.source = source = Source(eth_etherbone_description(32))
self.bus = bus = wishbone.Interface()
###
self.submodules.base_addr = base_addr = FlipFlop(32)
self.comb += self.base_addr.d.eq(self.sink.data)
self.submodules.counter = counter = Counter(32)
self.submodules.fifo = fifo = SyncFIFO([("data", 32)], 256)
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
sink.ack.eq(1),
counter.reset.eq(1),
If(sink.stb & sink.sop,
If(sink.wcount > 0,
self.base_addr.ce.eq(1),
NextState("WRITE_DATA")
).Elif(sink.rcount > 0,
self.base_addr.ce.eq(1),
NextState("READ_DATA")
)
)
)
fsm.act("WRITE_DATA",
bus.adr.eq(base_addr + self.counter.value),
bus.dat_w.eq(sink.data),
bus.sel.eq(0xf), # XXX?
bus.stb.eq(sink.stb),
bus.we.eq(1),
bus.cyc.eq(1),
If(bus.stb & bus.ack,
sink.ack.eq(1),
counter.ce.eq(1),
If(counter.value == sink.wcount-1,
If(sink.rcount > 0,
counter.reset.eq(1)
NextState("READ_DATA")
).Else(
NextState("TERMINATE")
)
)
)
)
fsm.act("CHECK_READ",
If(sink.rcount > 0,
If(sink.stb,
sink.ack.eq(1),
base_addr.ce.eq(1),
NextState("READ_DATA")
)
).Else(
NextState("IDLE")
)
)
fsm.act("READ_DATA",
bus.adr.eq(self.sink.data),
bus.sel.eq(0xf),
bus.stb.eq(1),
bus.we.eq(0),
bus.cyc.eq(1),
If(bus.stb & bus.ack,
sink.ack.eq(1),
counter.ce.eq(1),
fifo.sink.stb.eq(1),
fifo.sink.sop.eq(counter == 0),
fifo.sink.data.eq(bus.dat_r),
If(counter.value == sink.rcount-1,
fifo.sink.eop.eq(1),
NextState("PRESENT_DATA")
)
)
)
fsm.act("PRESENT_DATA",
source.stb.eq(fifo.stb),
source.sop.eq(fifo.sop),
source.eop.eq(fifo.eop),
fifo.ack.eq(source.ack),
source.length.eq(sink.rcount+1),
source.wcount.eq(sink.rcount),
source.rcount.eq(0),
If(source.stb & source.eop & source.ack,
NextState("IDLE")
)
)