drivers: clean up / fixes
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9a059336bf
commit
31e142fd88
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@ -52,7 +52,7 @@ class MiLaDriver():
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def build_mila(self):
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for key, value in self.regs.d.items():
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if self.name in key:
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if self.name == key[:len(self.name)]:
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key.replace(self.name, "mila")
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setattr(self, key, value)
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value = 1
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@ -97,24 +97,21 @@ class MiLaDriver():
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self.mila_trigger_sum_prog_dat.write(dat)
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self.mila_trigger_sum_prog_we.write(1)
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def enable_rle(self):
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self.mila_rle_enable.write(1)
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def disable_rle(self):
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self.mila_rle_enable.write(0)
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def config_rle(self, v):
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self.mila_rle_enable.write(v)
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def is_done(self):
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return self.mila_recorder_done.read()
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def wait_done(self):
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self.show_state("WAIT")
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self.show_state("WAIT HIT")
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while(not self.is_done()):
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time.sleep(0.1)
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def trigger(self, offset, length):
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self.show_state("TRIG")
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if self.use_rle:
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self.enable_rle()
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if self.with_rle:
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self.config_rle(self.use_rle)
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self.mila_recorder_offset.write(offset)
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self.mila_recorder_length.write(length)
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self.mila_recorder_trigger.write(1)
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@ -129,7 +126,7 @@ class MiLaDriver():
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if self.use_rle:
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self.dat = self.dat.decode_rle()
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if vcd:
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self.show_state("VCD", last=True)
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self.show_state("OUTPUT", last=True)
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_vcd = Vcd()
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_vcd.add_from_layout(self.layout, self.dat)
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_vcd.write(vcd)
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@ -18,9 +18,6 @@ class RunLengthEncoder(Module, AutoCSR):
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###
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enable = self._r_enable.storage
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fsm = FSM(reset_state="BYPASS")
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self.submodules += fsm
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sink_d = rec_dat(width)
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self.sync += If(self.sink.stb, sink_d.eq(self.sink))
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@ -41,6 +38,9 @@ class RunLengthEncoder(Module, AutoCSR):
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change = Signal()
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self.comb += change.eq(self.sink.stb & (self.sink.dat != sink_d.dat))
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fsm = FSM(reset_state="BYPASS")
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self.submodules += fsm
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fsm.act("BYPASS",
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sink_d.connect(self.source),
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cnt_reset.eq(1),
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