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https://github.com/enjoy-digital/litex.git
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s6ddrphy: use shorter Instance argument notation
Signed-off-by: Robert Jordens <jordens@gmail.com>
This commit is contained in:
Robert Jordens
Sebastien Bourdeauducq
parent
e4db7d1c7f
commit
31ec33dbad
1 changed files with 99 additions and 99 deletions
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@ -147,55 +147,55 @@ class S6DDRPHY(Module):
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for i in range(d//8):
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for i in range(d//8):
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# DQS output
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# DQS output
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self.specials += Instance("ODDR2",
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self.specials += Instance("ODDR2",
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Instance.Parameter("DDR_ALIGNMENT", dqs_ddr_alignment),
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p_DDR_ALIGNMENT=dqs_ddr_alignment,
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Instance.Parameter("INIT", 0),
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p_INIT=0,
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Instance.Parameter("SRTYPE", "ASYNC"),
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p_SRTYPE="ASYNC",
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Instance.Input("C0", sdram_half_clk),
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i_C0=sdram_half_clk,
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Instance.Input("C1", sdram_half_clk_n),
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i_C1=sdram_half_clk_n,
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Instance.Input("CE", 1),
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i_CE=1,
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Instance.Input("D0", 0),
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i_D0=0,
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Instance.Input("D1", 1),
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i_D1=1,
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Instance.Input("R", 0),
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i_R=0,
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Instance.Input("S", 0),
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i_S=0,
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Instance.Output("Q", dqs_o[i])
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o_Q=dqs_o[i]
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)
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)
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# DQS tristate cmd
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# DQS tristate cmd
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self.specials += Instance("ODDR2",
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self.specials += Instance("ODDR2",
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Instance.Parameter("DDR_ALIGNMENT", dqs_ddr_alignment),
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p_DDR_ALIGNMENT=dqs_ddr_alignment,
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Instance.Parameter("INIT", 0),
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p_INIT=0,
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Instance.Parameter("SRTYPE", "ASYNC"),
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p_SRTYPE="ASYNC",
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Instance.Input("C0", sdram_half_clk),
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i_C0=sdram_half_clk,
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Instance.Input("C1", sdram_half_clk_n),
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i_C1=sdram_half_clk_n,
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Instance.Input("CE", 1),
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i_CE=1,
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Instance.Input("D0", dqs_t_d0),
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i_D0=dqs_t_d0,
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Instance.Input("D1", dqs_t_d1),
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i_D1=dqs_t_d1,
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Instance.Input("R", 0),
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i_R=0,
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Instance.Input("S", 0),
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i_S=0,
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Instance.Output("Q", dqs_t[i])
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o_Q=dqs_t[i]
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)
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)
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# DQS tristate buffer
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# DQS tristate buffer
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if hasattr(pads, "dqs_n"):
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if hasattr(pads, "dqs_n"):
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self.specials += Instance("OBUFTDS",
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self.specials += Instance("OBUFTDS",
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Instance.Input("I", dqs_o[i]),
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i_I=dqs_o[i],
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Instance.Input("T", dqs_t[i]),
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i_T=dqs_t[i],
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Instance.Output("O", pads.dqs[i]),
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o_O=pads.dqs[i],
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Instance.Output("OB", pads.dqs_n[i]),
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o_OB=pads.dqs_n[i],
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)
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)
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else:
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else:
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self.specials += Instance("OBUFT",
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self.specials += Instance("OBUFT",
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Instance.Input("I", dqs_o[i]),
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i_I=dqs_o[i],
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Instance.Input("T", dqs_t[i]),
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i_T=dqs_t[i],
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Instance.Output("O", pads.dqs[i])
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o_O=pads.dqs[i]
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)
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)
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sd_sdram_half += postamble.eq(drive_dqs)
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sd_sdram_half += postamble.eq(drive_dqs)
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@ -234,68 +234,68 @@ class S6DDRPHY(Module):
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for i in range(d):
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for i in range(d):
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# Data serializer
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# Data serializer
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self.specials += Instance("OSERDES2",
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self.specials += Instance("OSERDES2",
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Instance.Parameter("DATA_WIDTH", 4),
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p_DATA_WIDTH=4,
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Instance.Parameter("DATA_RATE_OQ", "SDR"),
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p_DATA_RATE_OQ="SDR",
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Instance.Parameter("DATA_RATE_OT", "SDR"),
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p_DATA_RATE_OT="SDR",
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Instance.Parameter("SERDES_MODE", "NONE"),
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p_SERDES_MODE="NONE",
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Instance.Parameter("OUTPUT_MODE", "SINGLE_ENDED"),
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p_OUTPUT_MODE="SINGLE_ENDED",
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Instance.Output("OQ", dq_o[i]),
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o_OQ=dq_o[i],
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Instance.Input("OCE", 1),
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i_OCE=1,
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Instance.Input("CLK0", sdram_full_wr_clk),
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i_CLK0=sdram_full_wr_clk,
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Instance.Input("CLK1", 0),
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i_CLK1=0,
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Instance.Input("IOCE", self.clk4x_wr_strb),
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i_IOCE=self.clk4x_wr_strb,
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Instance.Input("RST", 0),
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i_RST=0,
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Instance.Input("CLKDIV", sys_clk),
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i_CLKDIV=sys_clk,
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Instance.Input("D1", dq_wrdata[wr_bitslip+3][i]),
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i_D1=dq_wrdata[wr_bitslip+3][i],
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Instance.Input("D2", dq_wrdata[wr_bitslip+2][i]),
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i_D2=dq_wrdata[wr_bitslip+2][i],
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Instance.Input("D3", dq_wrdata[wr_bitslip+1][i]),
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i_D3=dq_wrdata[wr_bitslip+1][i],
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Instance.Input("D4", dq_wrdata[wr_bitslip+0][i]),
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i_D4=dq_wrdata[wr_bitslip+0][i],
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Instance.Output("TQ", dq_t[i]),
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o_TQ=dq_t[i],
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Instance.Input("T1", drive_dq_n[(wr_bitslip+3)//4]),
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i_T1=drive_dq_n[(wr_bitslip+3)//4],
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Instance.Input("T2", drive_dq_n[(wr_bitslip+2)//4]),
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i_T2=drive_dq_n[(wr_bitslip+2)//4],
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Instance.Input("T3", drive_dq_n[(wr_bitslip+1)//4]),
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i_T3=drive_dq_n[(wr_bitslip+1)//4],
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Instance.Input("T4", drive_dq_n[(wr_bitslip+0)//4]),
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i_T4=drive_dq_n[(wr_bitslip+0)//4],
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Instance.Input("TRAIN", 0),
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i_TRAIN=0,
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Instance.Input("TCE", 1),
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i_TCE=1,
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Instance.Input("SHIFTIN1", 0),
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i_SHIFTIN1=0,
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Instance.Input("SHIFTIN2", 0),
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i_SHIFTIN2=0,
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Instance.Input("SHIFTIN3", 0),
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i_SHIFTIN3=0,
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Instance.Input("SHIFTIN4", 0),
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i_SHIFTIN4=0,
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)
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)
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# Data deserializer
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# Data deserializer
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self.specials += Instance("ISERDES2",
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self.specials += Instance("ISERDES2",
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Instance.Parameter("DATA_WIDTH", 4),
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p_DATA_WIDTH=4,
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Instance.Parameter("DATA_RATE", "SDR"),
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p_DATA_RATE="SDR",
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Instance.Parameter("BITSLIP_ENABLE", "TRUE"),
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p_BITSLIP_ENABLE="TRUE",
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Instance.Parameter("SERDES_MODE", "NONE"),
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p_SERDES_MODE="NONE",
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Instance.Parameter("INTERFACE_TYPE", "RETIMED"),
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p_INTERFACE_TYPE="RETIMED",
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Instance.Input("D", dq_i[i]),
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i_D=dq_i[i],
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Instance.Input("CE0", 1),
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i_CE0=1,
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Instance.Input("CLK0", sdram_full_rd_clk),
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i_CLK0=sdram_full_rd_clk,
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Instance.Input("CLK1", 0),
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i_CLK1=0,
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Instance.Input("IOCE", self.clk4x_rd_strb),
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i_IOCE=self.clk4x_rd_strb,
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Instance.Input("RST", ResetSignal()),
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i_RST=ResetSignal(),
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Instance.Input("CLKDIV", sys_clk),
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i_CLKDIV=sys_clk,
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Instance.Input("BITSLIP", bitslip_inc),
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i_BITSLIP=bitslip_inc,
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Instance.Output("Q1", d_dfi[0*nphases+0].rddata[i+d]),
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o_Q1=d_dfi[0*nphases+0].rddata[i+d],
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Instance.Output("Q2", d_dfi[0*nphases+0].rddata[i]),
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o_Q2=d_dfi[0*nphases+0].rddata[i],
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Instance.Output("Q3", d_dfi[0*nphases+1].rddata[i+d]),
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o_Q3=d_dfi[0*nphases+1].rddata[i+d],
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Instance.Output("Q4", d_dfi[0*nphases+1].rddata[i]),
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o_Q4=d_dfi[0*nphases+1].rddata[i],
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)
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)
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# Data buffer
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# Data buffer
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self.specials += Instance("IOBUF",
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self.specials += Instance("IOBUF",
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Instance.Input("I", dq_o[i]),
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i_I=dq_o[i],
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Instance.Output("O", dq_i[i]),
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o_O=dq_i[i],
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Instance.Input("T", dq_t[i]),
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i_T=dq_t[i],
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Instance.InOut("IO", pads.dq[i])
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io_IO=pads.dq[i]
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)
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)
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dq_wrdata_mask = []
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dq_wrdata_mask = []
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@ -307,31 +307,31 @@ class S6DDRPHY(Module):
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for i in range(d//8):
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for i in range(d//8):
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# Mask serializer
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# Mask serializer
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self.specials += Instance("OSERDES2",
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self.specials += Instance("OSERDES2",
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Instance.Parameter("DATA_WIDTH", 4),
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p_DATA_WIDTH=4,
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Instance.Parameter("DATA_RATE_OQ", "SDR"),
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p_DATA_RATE_OQ="SDR",
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Instance.Parameter("DATA_RATE_OT", "SDR"),
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p_DATA_RATE_OT="SDR",
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Instance.Parameter("SERDES_MODE", "NONE"),
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p_SERDES_MODE="NONE",
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Instance.Parameter("OUTPUT_MODE", "SINGLE_ENDED"),
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p_OUTPUT_MODE="SINGLE_ENDED",
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Instance.Output("OQ", pads.dm[i]),
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o_OQ=pads.dm[i],
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Instance.Input("OCE", 1),
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i_OCE=1,
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Instance.Input("CLK0", sdram_full_wr_clk),
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i_CLK0=sdram_full_wr_clk,
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Instance.Input("CLK1", 0),
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i_CLK1=0,
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Instance.Input("IOCE", self.clk4x_wr_strb),
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i_IOCE=self.clk4x_wr_strb,
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Instance.Input("RST", 0),
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i_RST=0,
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Instance.Input("CLKDIV", sys_clk),
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i_CLKDIV=sys_clk,
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Instance.Input("D1", dq_wrdata_mask[wr_bitslip+3][i]),
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i_D1=dq_wrdata_mask[wr_bitslip+3][i],
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Instance.Input("D2", dq_wrdata_mask[wr_bitslip+2][i]),
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i_D2=dq_wrdata_mask[wr_bitslip+2][i],
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Instance.Input("D3", dq_wrdata_mask[wr_bitslip+1][i]),
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i_D3=dq_wrdata_mask[wr_bitslip+1][i],
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Instance.Input("D4", dq_wrdata_mask[wr_bitslip+0][i]),
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i_D4=dq_wrdata_mask[wr_bitslip+0][i],
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Instance.Input("TRAIN", 0),
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i_TRAIN=0,
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Instance.Input("TCE", 0),
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i_TCE=0,
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Instance.Input("SHIFTIN1", 0),
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i_SHIFTIN1=0,
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Instance.Input("SHIFTIN2", 0),
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i_SHIFTIN2=0,
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Instance.Input("SHIFTIN3", 0),
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i_SHIFTIN3=0,
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Instance.Input("SHIFTIN4", 0),
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i_SHIFTIN4=0,
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)
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)
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#
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#
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