Merge pull request #1134 from fjullien/efinix_titanium_support
Efinix titanium support
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commit
321b91d551
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@ -65,24 +65,38 @@ class EfinixAsyncResetSynchronizer:
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class EfinixTristateImpl(Module):
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def __init__(self, platform, io, o, oe, i=None):
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nbits, sign = value_bits_sign(io)
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assert nbits == 1
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io_name = platform.get_pin_name(io)
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io_loc = platform.get_pin_location(io)
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io_o = platform.add_iface_io(io_name + "_OUT")
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io_oe = platform.add_iface_io(io_name + "_OE")
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io_i = platform.add_iface_io(io_name + "_IN")
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self.comb += io_o.eq(o)
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self.comb += io_oe.eq(oe)
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if i is not None:
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self.comb += i.eq(io_i)
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block = {
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"type" : "GPIO",
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"mode" : "INOUT",
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"name" : io_name,
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"location" : [io_loc[0]],
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(io_name)
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for bit in range(nbits):
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io_name = platform.get_pin_name(io[bit])
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io_loc = platform.get_pin_location(io[bit])
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io_prop = platform.get_pin_properties(io[bit])
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io_o = platform.add_iface_io(io_name + "_OUT")
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io_oe = platform.add_iface_io(io_name + "_OE")
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io_i = platform.add_iface_io(io_name + "_IN")
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self.comb += io_o.eq(o[bit])
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self.comb += io_oe.eq(oe)
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if i[bit] is not None:
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self.comb += i[bit].eq(io_i)
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block = {
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"type" : "GPIO",
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"mode" : "INOUT",
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"name" : io_name,
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"location" : [io_loc[0]],
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"properties" : io_prop
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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# Remove the group from the io list
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exclude = platform.get_pin_name(io[0], without_index=True)
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# In case of a single signal, there is still a '0' index
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# to be remove at the end
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if (nbits == 1) and (exclude[:-1] == '0'):
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exclude = exclude[:-1]
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platform.toolchain.excluded_ios.append(exclude)
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class EfinixTristate(Module):
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@staticmethod
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@ -115,6 +115,10 @@ def _format_constraint(c, signame, fmt_r, fragment, platform):
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prop = "DRIVE_STRENGTH"
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val = c.misc.split("=")[1]
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if "SLEWRATE" in c.misc:
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prop = "SLEW_RATE"
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val = "1"
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if prop == "":
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# Print error, warning ??
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return ""
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@ -108,6 +108,7 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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def generate_gpio(self, block, verbose=True):
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name = block["name"]
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mode = block["mode"]
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prop = block["properties"]
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cmd = ""
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if mode == "INOUT":
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@ -118,6 +119,9 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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cmd += f'design.create_inout_gpio("{name}",{block["size"]-1},0)\n'
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for i, pad in enumerate(block["location"]):
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cmd += f'design.assign_pkg_pin("{name}[{i}]","{pad}")\n'
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if prop:
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for p, val in prop:
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cmd += 'design.set_property("{}","{}","{}")\n'.format(name, p, val)
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cmd += "\n"
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return cmd
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@ -132,6 +136,10 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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if "in_reg" in block:
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cmd += f'design.set_property("{name}","IN_REG","{block["in_reg"]}")\n'
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cmd += f'design.set_property("{name}","IN_CLK_PIN","{block["in_clk_pin"]}")\n'
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if prop:
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for p, val in prop:
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cmd += 'design.set_property("{}","{}","{}")\n'.format(name, p, val)
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cmd += "\n"
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return cmd
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if mode == "OUTPUT":
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@ -150,6 +158,9 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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if "drive_strength" in block:
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cmd += 'design.set_property("{}","DRIVE_STRENGTH","4")\n'.format(name, block["drive_strength"])
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if prop:
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for p, val in prop:
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cmd += 'design.set_property("{}","{}","{}")\n'.format(name, p, val)
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cmd += "\n"
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return cmd
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@ -157,12 +168,20 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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cmd += 'design.create_input_clock_gpio("{}")\n'.format(name)
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cmd += 'design.set_property("{}","IN_PIN","{}")\n'.format(name, name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n\n'.format(name, block["location"])
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if prop:
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for p, val in prop:
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cmd += 'design.set_property("{}","{}","{}")\n'.format(name, p, val)
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cmd += "\n"
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return cmd
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if mode == "OUTPUT_CLK":
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cmd += 'design.create_clockout_gpio("{}")\n'.format(name)
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cmd += 'design.set_property("{}","OUT_CLK_PIN","{}")\n'.format(name, name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n\n'.format(name, block["location"])
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if prop:
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for p, val in prop:
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cmd += 'design.set_property("{}","{}","{}")\n'.format(name, p, val)
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cmd += "\n"
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return cmd
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cmd = "# TODO: " + str(block) +"\n"
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@ -86,7 +86,36 @@ class EfinixPlatform(GenericPlatform):
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return [pins[idx]]
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return None
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def get_pin_name(self, sig):
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def get_pin_properties(self, sig):
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ret = []
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if sig is None:
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return None
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assert len(sig) == 1
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if isinstance(sig, _Slice):
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sig = sig.value
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sc = self.constraint_manager.get_sig_constraints()
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for s, pins, others, resource in sc:
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if (s == sig) and (pins[0] != 'X'):
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for o in others:
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if isinstance(o, IOStandard):
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ret.append(('IO_STANDARD', o.name))
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if isinstance(o, Misc):
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if o.misc in ["WEAK_PULLUP", "WEAK_PULLDOWN"]:
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prop = "PULL_OPTION"
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val = o.misc
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if "DRIVE_STRENGTH" in o.misc:
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prop = "DRIVE_STRENGTH"
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val = o.misc.split("=")[1]
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ret.append((prop, val))
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if "SLEWRATE" in o.misc:
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prop = "SLEW_RATE"
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val = "1"
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ret.append((prop, val))
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return ret
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return None
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def get_pin_name(self, sig, without_index=False):
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if sig is None:
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return None
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assert len(sig) == 1
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@ -100,7 +129,10 @@ class EfinixPlatform(GenericPlatform):
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for s, pins, others, resource in sc:
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if s == sig:
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if resource[2]:
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return resource[0] + "_" + resource[2] + (f"{idx}" if slc else "")
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name = resource[0] + "_" + resource[2]
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if without_index is False:
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name = name + (f"{idx}" if slc else "")
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return name
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else:
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return resource[0] + (f"{idx}" if slc else "")
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return None
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