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Merge pull request #992 from cklarhorst/master 

cores/vexriscv_smp: Fix vexriscv_smp doesn't build without a memory bus
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enjoy-digital 2021-08-13 09:46:51 +02:00 committed by GitHub
parent ab9f214a5e ebe22ca2b6
commit 32b913b362
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1 changed files with 1 additions and 2 deletions
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litex/soc/cores/cpu/vexriscv_smp/core.py Normal file → Executable file
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@ -419,8 +419,6 @@ class VexRiscvSMP(CPU):
def add_memory_buses(self, address_width, data_width): def add_memory_buses(self, address_width, data_width):
VexRiscvSMP.litedram_width = data_width VexRiscvSMP.litedram_width = data_width
VexRiscvSMP.generate_cluster_name()
from litedram.common import LiteDRAMNativePort from litedram.common import LiteDRAMNativePort
if(not VexRiscvSMP.wishbone_memory): if(not VexRiscvSMP.wishbone_memory):
ibus = LiteDRAMNativePort(mode="both", address_width=32, data_width=VexRiscvSMP.litedram_width) ibus = LiteDRAMNativePort(mode="both", address_width=32, data_width=VexRiscvSMP.litedram_width)
@ -457,6 +455,7 @@ class VexRiscvSMP(CPU):
def do_finalize(self): def do_finalize(self):
assert hasattr(self, "reset_address") assert hasattr(self, "reset_address")
VexRiscvSMP.generate_cluster_name()
self.specials += Instance(self.cluster_name, **self.cpu_params) self.specials += Instance(self.cluster_name, **self.cpu_params)
# Add Verilog sources # Add Verilog sources