Merge pull request #992 from cklarhorst/master
cores/vexriscv_smp: Fix vexriscv_smp doesn't build without a memory bus
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32b913b362
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@ -419,8 +419,6 @@ class VexRiscvSMP(CPU):
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def add_memory_buses(self, address_width, data_width):
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VexRiscvSMP.litedram_width = data_width
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VexRiscvSMP.generate_cluster_name()
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from litedram.common import LiteDRAMNativePort
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if(not VexRiscvSMP.wishbone_memory):
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ibus = LiteDRAMNativePort(mode="both", address_width=32, data_width=VexRiscvSMP.litedram_width)
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@ -457,6 +455,7 @@ class VexRiscvSMP(CPU):
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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VexRiscvSMP.generate_cluster_name()
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self.specials += Instance(self.cluster_name, **self.cpu_params)
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# Add Verilog sources
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