SATAPHYDatapathRX: use Converter and simplify
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@ -11,45 +11,26 @@ class SATAPHYDatapathRX(Module):
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###
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###
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# bytes alignment
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# width convertion (16 to 32) and byte alignment
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last_charisk = Signal(2)
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# shift register
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last_data = Signal(16)
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data_sr = Signal(32+8)
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self.sync += \
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charisk_sr = Signal(4+1)
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If(self.sink.stb & self.sink.ack,
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data_sr_d = Signal(32+8)
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If(self.sink.charisk != 0,
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charisk_sr_d = Signal(4+1)
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last_charisk.eq(self.sink.charisk)
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self.comb += [
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),
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data_sr.eq(Cat(data_sr_d[16:], self.sink.data)),
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last_data.eq(self.sink.data)
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charisk_sr.eq(Cat(charisk_sr_d[2:], self.sink.charisk))
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]
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self.sync.sata_rx += [
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data_sr_d.eq(data_sr),
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charisk_sr_d.eq(charisk_sr)
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]
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# alignment
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alignment = Signal()
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valid = Signal()
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self.sync.sata_rx += [
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If(self.sink.charisk !=0,
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alignment.eq(self.sink.charisk[1]),
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valid.eq(0)
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).Else(
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valid.eq(~valid)
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)
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)
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]
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self.converter = Converter(phy_description(16), phy_description(32), reverse=True)
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# 16 to 32
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data = Signal(32)
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charisk = Signal(4)
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self.comb += [
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self.comb += [
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If(alignment,
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self.converter.sink.stb.eq(self.sink.stb),
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data.eq(data_sr[0:32]),
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self.converter.sink.charisk.eq(0b01),
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charisk.eq(charisk_sr[0:4])
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If(last_charisk[1],
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self.converter.sink.data.eq(Cat(self.sink.data[8:], last_data[:8]))
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).Else(
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).Else(
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data.eq(data_sr[8:40]),
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self.converter.sink.data.eq(self.sink.data)
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charisk.eq(charisk_sr[1:5])
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),
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)
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self.sink.ack.eq(self.converter.sink.ack)
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]
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]
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# clock domain crossing
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# clock domain crossing
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@ -62,12 +43,9 @@ class SATAPHYDatapathRX(Module):
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fifo = AsyncFIFO(phy_description(32), 4)
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fifo = AsyncFIFO(phy_description(32), 4)
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self.fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"})
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self.fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"})
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self.comb += [
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self.comb += [
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fifo.sink.stb.eq(valid),
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Record.connect(self.converter.source, fifo.sink),
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fifo.sink.data.eq(data),
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Record.connect(fifo.source, self.source)
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fifo.sink.charisk.eq(charisk),
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self.sink.ack.eq(fifo.sink.ack)
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]
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]
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self.comb += Record.connect(fifo.source, self.source)
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class SATAPHYDatapathTX(Module):
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class SATAPHYDatapathTX(Module):
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def __init__(self):
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def __init__(self):
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@ -84,7 +62,7 @@ class SATAPHYDatapathTX(Module):
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# source destination is always able to accept data (ack always 1)
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# source destination is always able to accept data (ack always 1)
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fifo = AsyncFIFO(phy_description(32), 4)
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fifo = AsyncFIFO(phy_description(32), 4)
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self.fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"})
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self.fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"})
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self.comb += Record.connect(self.sink, fifo.sink),
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self.comb += Record.connect(self.sink, fifo.sink)
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# width convertion (32 to 16)
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# width convertion (32 to 16)
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self.converter = Converter(phy_description(32), phy_description(16), reverse=True)
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self.converter = Converter(phy_description(32), phy_description(16), reverse=True)
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@ -55,11 +55,11 @@ class TB(Module):
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]
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]
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self.streamer = DataStreamer()
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self.streamer = DataStreamer()
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self.streamer_randomizer = Randomizer(phy_description(32), level=0)
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self.streamer_randomizer = Randomizer(phy_description(32), level=10)
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self.trx = TRX()
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self.trx = TRX()
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self.ctrl = CTRL()
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self.ctrl = CTRL()
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self.datapath = SATAPHYDatapath(self.trx, self.ctrl)
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self.datapath = SATAPHYDatapath(self.trx, self.ctrl)
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self.logger_randomizer = Randomizer(phy_description(32), level=0)
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self.logger_randomizer = Randomizer(phy_description(32), level=10)
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self.logger = DataLogger()
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self.logger = DataLogger()
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self.pipeline = Pipeline(
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self.pipeline = Pipeline(
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