fsm: NextState and NextValue should derive from _Statement
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@ -1,7 +1,7 @@
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from collections import OrderedDict
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Slice, _ArrayProxy
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from migen.fhdl.structure import _Statement, _Slice, _ArrayProxy
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from migen.fhdl.module import Module, FinalizeError
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from migen.fhdl.visit import NodeTransformer
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from migen.fhdl.bitcontainer import value_bits_sign
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@ -16,12 +16,12 @@ class AnonymousState:
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# do not use namedtuple here as it inherits tuple
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# and the latter is used elsewhere in FHDL
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class NextState:
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class NextState(_Statement):
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def __init__(self, state):
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self.state = state
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class NextValue:
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class NextValue(_Statement):
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def __init__(self, target, value):
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self.target = target
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self.value = value
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