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interconnect/stream/ClockDomainCrossing: Use DUID for clock_domain id to allow deterministic builds.

This commit is contained in:
Florent Kermarrec 2023-11-06 16:49:54 +01:00
parent ef4235a5d9
commit 33fd7742c9
1 changed files with 3 additions and 2 deletions
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5
litex/soc/interconnect/stream.py
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@ -244,8 +244,9 @@ class AsyncFIFO(_FIFOWrapper):
# ClockDomainCrossing ------------------------------------------------------------------------------ # ClockDomainCrossing ------------------------------------------------------------------------------
class ClockDomainCrossing(LiteXModule): class ClockDomainCrossing(LiteXModule, DUID):
def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, buffered=False, with_common_rst=False): def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, buffered=False, with_common_rst=False):
DUID.__init__(self)
self.sink = Endpoint(layout) self.sink = Endpoint(layout)
self.source = Endpoint(layout) self.source = Endpoint(layout)
@ -259,7 +260,7 @@ class ClockDomainCrossing(LiteXModule):
else: else:
if with_common_rst: if with_common_rst:
# Create intermediate Clk Domains and generate a common Rst. # Create intermediate Clk Domains and generate a common Rst.
_cd_id = id(self) # FIXME: Improve, used to allow build with anonymous modules. _cd_id = self.duid # Use duid for a deterministic unique ID.
_cd_rst = Signal() _cd_rst = Signal()
_cd_from = ClockDomain(f"from{_cd_id}") _cd_from = ClockDomain(f"from{_cd_id}")
_cd_to = ClockDomain(f"to{_cd_id}") _cd_to = ClockDomain(f"to{_cd_id}")