targets: revert use of integers in clocks/timings
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9137b91e9e
commit
340014dbac
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@ -15,7 +15,7 @@ class _CRG(Module):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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f0 = 32*1e6
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f0 = 32*1000000
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clk32 = platform.request("clk32")
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clk32 = platform.request("clk32")
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clk32a = Signal()
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clk32a = Signal()
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self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
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self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
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@ -35,7 +35,7 @@ class _CRG(Module):
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
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i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
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p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
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p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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@ -64,7 +64,7 @@ class BaseSoC(SDRAMSoC):
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default_platform = "minispartan6"
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default_platform = "minispartan6"
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def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
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def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
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clk_freq = 80*1e6
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clk_freq = 80*1000000
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SDRAMSoC.__init__(self, platform, clk_freq,
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SDRAMSoC.__init__(self, platform, clk_freq,
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with_integrated_rom=True,
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with_integrated_rom=True,
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sdram_controller_settings=sdram_controller_settings,
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sdram_controller_settings=sdram_controller_settings,
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@ -20,7 +20,7 @@ class _CRG(Module):
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self.clk4x_wr_strb = Signal()
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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self.clk4x_rd_strb = Signal()
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f0 = 50*1e6
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f0 = 50*1000000
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clk50 = platform.request("clk50")
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clk50 = platform.request("clk50")
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clk50a = Signal()
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clk50a = Signal()
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self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
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self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
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@ -41,7 +41,7 @@ class _CRG(Module):
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1,
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i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1,
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p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
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p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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@ -91,7 +91,7 @@ class BaseSoC(SDRAMSoC):
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csr_map.update(SDRAMSoC.csr_map)
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csr_map.update(SDRAMSoC.csr_map)
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def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
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def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
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clk_freq = 75*1e6
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clk_freq = 75*1000000
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if not kwargs.get("with_integrated_rom"):
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if not kwargs.get("with_integrated_rom"):
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kwargs["rom_size"] = 0x1000000 # 128 Mb
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kwargs["rom_size"] = 0x1000000 # 128 Mb
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SDRAMSoC.__init__(self, platform, clk_freq,
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SDRAMSoC.__init__(self, platform, clk_freq,
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@ -15,7 +15,7 @@ class _CRG(Module):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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f0 = 32*1e6
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f0 = 32*1000000
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clk32 = platform.request("clk32")
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clk32 = platform.request("clk32")
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clk32a = Signal()
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clk32a = Signal()
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self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
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self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
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@ -35,7 +35,7 @@ class _CRG(Module):
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
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i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
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p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
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p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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@ -69,7 +69,7 @@ class BaseSoC(SDRAMSoC):
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csr_map.update(SDRAMSoC.csr_map)
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csr_map.update(SDRAMSoC.csr_map)
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def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
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def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
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clk_freq = 80*1e6
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clk_freq = 80*1000000
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SDRAMSoC.__init__(self, platform, clk_freq,
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SDRAMSoC.__init__(self, platform, clk_freq,
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cpu_reset_address=0x60000,
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cpu_reset_address=0x60000,
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sdram_controller_settings=sdram_controller_settings,
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sdram_controller_settings=sdram_controller_settings,
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