clock/lattice_ecp5/ECP5PLL: implement 4-output solver
Reimplement the configuration loop to allow all 4 outputs to be used by the user, if one of them is suitable for use as VCO feedback. The new strategy is to first iterate over requested outputs to see if any of them can be used as a feedback source. If one can, it is selected, and if no output is suitable, it attempts to instantiate one. Once the feedback path is selected, the VCO frequency is known and it attempts to calculate the remaining outputs' settings. In addition, this implementation now respects datasheet limits in two new ways: - It respects the post-input-divider minimum frequency of 10MHz - It respects the max output frequency of 400MHz for instantiated feedback outputs I am slightly unhappy with the seemingly-repetitive for loops. However each one has slightly different sematics and I don't see a way to combine them that doesn't hinder readability.
This commit is contained in:
George Hilliard
parent
8b9f03efba
commit
34ba649f38
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@ -2,6 +2,7 @@
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# This file is part of LiteX.
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#
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# Copyright (c) 2018-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 George Hilliard <thirtythreeforty@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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@ -12,13 +13,14 @@ from litex.soc.cores.clock.common import *
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# Lattice / ECP5 -----------------------------------------------------------------------------------
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class ECP5PLL(Module):
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nclkouts_max = 3
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nclkouts_max = 4
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clki_div_range = (1, 128+1)
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clkfb_div_range = (1, 128+1)
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clko_div_range = (1, 128+1)
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clki_freq_range = ( 8e6, 400e6)
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clko_freq_range = (3.125e6, 400e6)
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vco_freq_range = ( 400e6, 800e6)
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pfd_freq_range = ( 10e6, 400e6)
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def __init__(self):
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self.logger = logging.getLogger("ECP5PLL")
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@ -60,29 +62,66 @@ class ECP5PLL(Module):
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def compute_config(self):
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config = {}
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def in_range(n, r):
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(r_min, r_max) = r
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return n >= r_min and n <= r_max
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def found_clk(n, f, d, p):
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config["clko{}_freq".format(n)] = f
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config["clko{}_div".format(n)] = d
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config["clko{}_phase".format(n)] = p
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for clki_div in range(*self.clki_div_range):
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if not in_range(self.clkin_freq / clki_div, self.pfd_freq_range):
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continue
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config["clki_div"] = clki_div
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for clkfb_div in range(*self.clkfb_div_range):
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all_valid = True
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vco_freq = self.clkin_freq/clki_div*clkfb_div*1 # clkos3_div=1
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max:
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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valid = False
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for d in range(*self.clko_div_range):
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clk_freq = vco_freq/d
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if abs(clk_freq - f) <= f*m:
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config["clko{}_freq".format(n)] = clk_freq
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config["clko{}_div".format(n)] = d
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config["clko{}_phase".format(n)] = p
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valid = True
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break
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if not valid:
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all_valid = False
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# pick a suitable feedback clock
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found_fb = None
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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for d in range(*self.clko_div_range):
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vco_freq = self.clkin_freq/clki_div*clkfb_div*d
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clk_freq = vco_freq/d
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if in_range(vco_freq, self.vco_freq_range) \
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and abs(clk_freq - f) <= f*m:
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found_fb = n
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found_clk(n, f, d, p)
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break
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if found_fb is not None:
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break
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else:
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all_valid = False
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# none found, try to use a new output
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for d in range(*self.clko_div_range):
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vco_freq = self.clkin_freq/clki_div*clkfb_div*d
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clk_freq = vco_freq/d
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if self.nclkouts < self.nclkouts_max \
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and in_range(vco_freq, self.vco_freq_range) \
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and in_range(clk_freq, self.clko_freq_range):
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found_fb = self.nclkouts
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found_clk(found_fb, clk_freq, d, 0)
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break
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else:
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continue
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# vco_freq is known, compute remaining clocks' output settings
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all_valid = True
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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if n == found_fb:
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continue # already picked this one
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for d in range(*self.clko_div_range):
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clk_freq = vco_freq/d
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if abs(clk_freq - f) <= f*m:
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found_clk(n, f, d, p)
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break
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else:
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all_valid = False
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if all_valid:
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if found_fb > self.nclkouts:
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self.create_clkout(ClockDomain('feedback'), vco_freq / clkfb_div)
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config["vco"] = vco_freq
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config["clkfb"] = found_fb
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config["clkfb_div"] = clkfb_div
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compute_config_log(self.logger, config)
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return config
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@ -107,8 +146,8 @@ class ECP5PLL(Module):
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def do_finalize(self):
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config = self.compute_config()
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clkfb = Signal()
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locked = Signal()
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n_to_l = {0: "P", 1: "S", 2: "S2", 3: "S3"}
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self.params.update(
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attr=[
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("FREQUENCY_PIN_CLKI", str(self.clkin_freq/1e6)),
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@ -120,17 +159,12 @@ class ECP5PLL(Module):
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i_CLKI = self.clkin,
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i_STDBY = self.stdby,
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o_LOCK = locked,
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p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for feedback with div=1.
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p_CLKOS3_ENABLE = "ENABLED",
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p_CLKOS3_DIV = 1,
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p_CLKOS3_FPHASE = 0,
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p_CLKOS3_CPHASE = 23,
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p_FEEDBK_PATH = "INT_O{}".format(n_to_l[config['clkfb']]),
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p_CLKFB_DIV = config["clkfb_div"],
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p_CLKI_DIV = config["clki_div"]
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)
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self.comb += self.locked.eq(locked & ~self.reset)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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n_to_l = {0: "P", 1: "S", 2: "S2"}
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div = config["clko{}_div".format(n)]
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cphase = int(p*(div + 1)/360 + div - 1)
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self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
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