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cores/timer/uart: Use edge="rising on Timer/UART's EventSourceProcess. 

Make code easier to understand.
This commit is contained in:
Florent Kermarrec 2021-05-27 18:47:40 +02:00
parent 5fd215fe3a
commit 34df454157
2 changed files with 8 additions and 8 deletions
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4
litex/soc/cores/timer.py
View File

@ -66,7 +66,7 @@ class Timer(Module, AutoCSR, AutoDoc):
This value is updated by writing to ``update_value``.""") This value is updated by writing to ``update_value``.""")
self.submodules.ev = EventManager() self.submodules.ev = EventManager()
self.ev.zero = EventSourceProcess() self.ev.zero = EventSourceProcess(edge="rising")
self.ev.finalize() self.ev.finalize()
# # # # # #
@ -85,7 +85,7 @@ class Timer(Module, AutoCSR, AutoDoc):
), ),
If(self._update_value.re, self._value.status.eq(value)) If(self._update_value.re, self._value.status.eq(value))
] ]
self.comb += self.ev.zero.trigger.eq(value != 0) self.comb += self.ev.zero.trigger.eq(value == 0)
def add_uptime(self, width=64): def add_uptime(self, width=64):
if self.with_uptime: return if self.with_uptime: return

12
litex/soc/cores/uart.py
View File

@ -221,8 +221,8 @@ class UART(Module, AutoCSR, UARTInterface):
self._rxempty = CSRStatus() self._rxempty = CSRStatus()
self.submodules.ev = EventManager() self.submodules.ev = EventManager()
self.ev.tx = EventSourceProcess() self.ev.tx = EventSourceProcess(edge="rising")
self.ev.rx = EventSourceProcess() self.ev.rx = EventSourceProcess(edge="rising")
self.ev.finalize() self.ev.finalize()
self._txempty = CSRStatus() self._txempty = CSRStatus()
@ -249,8 +249,8 @@ class UART(Module, AutoCSR, UARTInterface):
self._txfull.status.eq(~tx_fifo.sink.ready), self._txfull.status.eq(~tx_fifo.sink.ready),
self._txempty.status.eq(~tx_fifo.source.valid), self._txempty.status.eq(~tx_fifo.source.valid),
tx_fifo.source.connect(self.source), tx_fifo.source.connect(self.source),
# Generate TX IRQ when tx_fifo becomes non-full # Generate TX IRQ when tx_fifo becomes non-full.
self.ev.tx.trigger.eq(~tx_fifo.sink.ready) self.ev.tx.trigger.eq(tx_fifo.sink.ready)
] ]
# RX # RX
@ -263,8 +263,8 @@ class UART(Module, AutoCSR, UARTInterface):
self._rxfull.status.eq(~rx_fifo.sink.ready), self._rxfull.status.eq(~rx_fifo.sink.ready),
self._rxtx.w.eq(rx_fifo.source.data), self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ready.eq(self.ev.rx.clear | (rx_fifo_rx_we & self._rxtx.we)), rx_fifo.source.ready.eq(self.ev.rx.clear | (rx_fifo_rx_we & self._rxtx.we)),
# Generate RX IRQ when rx_fifo becomes non-empty # Generate RX IRQ when rx_fifo becomes non-empty.
self.ev.rx.trigger.eq(~rx_fifo.source.valid) self.ev.rx.trigger.eq(rx_fifo.source.valid)
] ]
# UART Bone ---------------------------------------------------------------------------------------- # UART Bone ----------------------------------------------------------------------------------------