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soc: allow passing custom CPU class to SoC. 

Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
This commit is contained in:
Florent Kermarrec 2020-04-29 20:11:47 +02:00
parent 90a6343df1
commit 3531a64173
2 changed files with 6 additions and 2 deletions
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5
litex/soc/integration/soc.py
View File

@ -762,7 +762,7 @@ class SoC(Module):
self.add_config("CSR_DATA_WIDTH", self.csr.data_width) self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
self.add_config("CSR_ALIGNMENT", self.csr.alignment) self.add_config("CSR_ALIGNMENT", self.csr.alignment)
def add_cpu(self, name="vexriscv", variant="standard", reset_address=None): def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None):
if name not in cpu.CPUS.keys(): if name not in cpu.CPUS.keys():
self.logger.error("{} CPU {}, supporteds: {}".format( self.logger.error("{} CPU {}, supporteds: {}".format(
colorer(name), colorer(name),
@ -770,7 +770,8 @@ class SoC(Module):
colorer(", ".join(cpu.CPUS.keys())))) colorer(", ".join(cpu.CPUS.keys()))))
raise raise
# Add CPU # Add CPU
self.submodules.cpu = cpu.CPUS[name](self.platform, variant) cpu_cls = cls if cls is not None else cpu.CPUS[name]
self.submodules.cpu = cpu_cls(self.platform, variant)
# Update SoC with CPU constraints # Update SoC with CPU constraints
for n, (origin, size) in enumerate(self.cpu.io_regions.items()): for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False)) self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))

3
litex/soc/integration/soc_core.py
View File

@ -65,6 +65,7 @@ class SoCCore(LiteXSoC):
cpu_type = "vexriscv", cpu_type = "vexriscv",
cpu_reset_address = None, cpu_reset_address = None,
cpu_variant = None, cpu_variant = None,
cpu_cls = None,
# ROM parameters # ROM parameters
integrated_rom_size = 0, integrated_rom_size = 0,
integrated_rom_init = [], integrated_rom_init = [],
@ -131,6 +132,7 @@ class SoCCore(LiteXSoC):
self.cpu_type = cpu_type self.cpu_type = cpu_type
self.cpu_variant = cpu_variant self.cpu_variant = cpu_variant
self.cpu_cls = cpu_cls
self.integrated_rom_size = integrated_rom_size self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != [] self.integrated_rom_initialized = integrated_rom_init != []
@ -154,6 +156,7 @@ class SoCCore(LiteXSoC):
self.add_cpu( self.add_cpu(
name = str(cpu_type), name = str(cpu_type),
variant = "standard" if cpu_variant is None else cpu_variant, variant = "standard" if cpu_variant is None else cpu_variant,
cls = cpu_cls,
reset_address = None if integrated_rom_size else cpu_reset_address) reset_address = None if integrated_rom_size else cpu_reset_address)
# Add User's interrupts # Add User's interrupts