actorlib: WB reader simulation OK
This commit is contained in:
Sebastien Bourdeauducq
parent
11674242c4
commit
356051e8a8
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@ -1,27 +1,97 @@
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import networkx as nx
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from random import Random
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from migen.fhdl import verilog
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from migen.flow.ala import *
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from migen.flow.network import *
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from migen.actorlib import dma_wishbone, control
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from migen.actorlib import dma_wishbone
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from migen.actorlib.sim import *
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from migen.bus import wishbone
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from migen.sim.generic import Simulator
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from migen.sim.icarus import Runner
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L = [
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("x", BV(10), 8),
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("y", BV(10), 8),
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("level2", [
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("a", BV(5), 32),
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("b", BV(5), 16)
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])
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]
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class MyPeripheral:
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def __init__(self):
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self.bus = wishbone.Interface()
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self.ack_en = Signal()
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self.prng = Random(763627)
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adrgen = control.For(10)
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reader = dma_wishbone.Reader(L)
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def do_simulation(self, s):
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# Only authorize acks on certain cycles to simulate variable latency.
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s.wr(self.ack_en, self.prng.randrange(0, 2))
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g = nx.MultiDiGraph()
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add_connection(g, adrgen, reader)
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comp = CompositeActor(g)
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def get_fragment(self):
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comb = [
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self.bus.ack.eq(self.bus.cyc & self.bus.stb & self.ack_en),
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self.bus.dat_r.eq(self.bus.adr + 4)
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]
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return Fragment(comb, sim=[self.do_simulation])
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frag = comp.get_fragment()
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ios = set(reader.bus.signals())
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ios.add(comp.busy)
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print(verilog.convert(frag, ios=ios))
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def adrgen_gen():
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for i in range(10):
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print("Address: " + str(i))
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yield Token("address", {"a": i})
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def dumper_gen():
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while True:
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t = Token("data")
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yield t
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print("Received: " + str(t.value["d"]))
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def test_reader():
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print("*** Testing reader")
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adrgen = SimActor(adrgen_gen(), ("address", Source, [("a", BV(30))]))
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reader = dma_wishbone.Reader()
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dumper = SimActor(dumper_gen(), ("data", Sink, [("d", BV(32))]))
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g = nx.MultiDiGraph()
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add_connection(g, adrgen, reader)
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add_connection(g, reader, dumper)
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comp = CompositeActor(g)
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peripheral = MyPeripheral()
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interconnect = wishbone.InterconnectPointToPoint(reader.bus, peripheral.bus)
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def end_simulation(s):
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s.interrupt = adrgen.done and not s.rd(comp.busy)
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fragment = comp.get_fragment() \
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+ peripheral.get_fragment() \
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+ interconnect.get_fragment() \
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+ Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner())
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sim.run()
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def trgen_gen():
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for i in range(10):
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a = i
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d = i+10
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print("Address: " + str(a) + " Data: " + str(d))
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yield Token("address_data", {"a": a, "d": d})
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def test_writer():
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print("*** Testing writer")
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trgen = SimActor(trgen_gen(), ("address_data", Source, [("a", BV(30)), ("d", BV(32))]))
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writer = dma_wishbone.Reader()
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g = nx.MultiDiGraph()
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add_connection(g, trgen, writer)
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comp = CompositeActor(g)
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peripheral = MyPeripheral()
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tap = wishbone.Tap(peripheral.bus)
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interconnect = wishbone.InterconnectPointToPoint(writer.bus, peripheral.bus)
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def end_simulation(s):
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s.interrupt = trgen.done and not s.rd(comp.busy)
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fragment = comp.get_fragment() \
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+ peripheral.get_fragment() \
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+ tap.get_fragment() \
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+ interconnect.get_fragment() \
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+ Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner())
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sim.run()
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test_reader()
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test_writer()
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@ -1,86 +1,58 @@
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from migen.fhdl.structure import *
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from migen.corelogic.record import *
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from migen.corelogic.fsm import *
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from migen.bus import wishbone
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from migen.flow.actor import *
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class Reader(Actor):
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def __init__(self, layout):
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self.bus = wishbone.Master()
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Actor.__init__(self,
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SchedulingModel(SchedulingModel.DYNAMIC),
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def __init__(self):
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self.bus = wishbone.Interface()
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super().__init__(
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("address", Sink, [("a", BV(30))]),
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("data", Source, layout))
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("data", Source, [("d", BV(32))]))
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def get_fragment(self):
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components, length = self.token("data").flatten(align=True, return_offset=True)
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nwords = (length + 31)//32
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bus_stb = Signal()
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# Address generator
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ag_stb = Signal()
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ag_sync = [If(ag_stb, self.bus.adr_o.eq(self.token("address").a))]
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if nwords > 1:
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ag_inc = Signal()
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ag_sync.append(If(ag_inc, self.bus.adr_o.eq(self.bus.adr_o + 1)))
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address_generator = Fragment(sync=ag_sync)
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data_reg_loaded = Signal()
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data_reg = Signal(BV(32))
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# Output buffer
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ob_reg = Signal(BV(length))
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ob_stbs = Signal(BV(nwords))
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ob_sync = []
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top = length
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for w in range(nwords):
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if top >= 32:
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width = 32
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sl = self.bus.dat_i
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else:
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width = top
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sl = self.bus.dat_i[32-top:]
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ob_sync.append(If(ob_stbs[w],
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ob_reg[top-width:top].eq(sl)))
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top -= width
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ob_comb = []
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offset = 0
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for s in components:
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w = s.bv.width
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if isinstance(s, Signal):
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ob_comb.append(s.eq(ob_reg[length-offset-w:length-offset]))
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offset += w
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output_buffer = Fragment(ob_comb, ob_sync)
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# Controller
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fetch_states = ["FETCH{0}".format(w) for w in range(nwords)]
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states = ["IDLE"] + fetch_states + ["STROBE"]
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fsm = FSM(*states)
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self.busy.reset = Constant(1)
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fsm.act(fsm.IDLE,
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self.busy.eq(0),
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ag_stb.eq(1),
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self.endpoints["address"].ack.eq(1),
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If(self.endpoints["address"].stb, fsm.next_state(fsm.FETCH0))
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)
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for w in range(nwords):
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state = getattr(fsm, fetch_states[w])
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if w == nwords - 1:
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next_state = fsm.STROBE
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else:
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next_state = getattr(fsm, fetch_states[w+1])
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fsm.act(state,
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self.bus.cyc_o.eq(1),
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self.bus.stb_o.eq(1),
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ob_stbs[w].eq(1),
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If(self.bus.ack_i,
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fsm.next_state(next_state),
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ag_inc.eq(1) if nwords > 1 else None
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)
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comb = [
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self.busy.eq(data_reg_loaded),
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self.bus.we.eq(0),
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bus_stb.eq(self.endpoints["address"].stb & (~data_reg_loaded | self.endpoints["data"].ack)),
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self.bus.cyc.eq(bus_stb),
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self.bus.stb.eq(bus_stb),
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self.bus.adr.eq(self.token("address").a),
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self.endpoints["address"].ack.eq(self.bus.ack),
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self.endpoints["data"].stb.eq(data_reg_loaded),
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self.token("data").d.eq(data_reg)
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]
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sync = [
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If(self.endpoints["data"].ack,
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data_reg_loaded.eq(0)
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),
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If(self.bus.ack,
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data_reg_loaded.eq(1),
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data_reg.eq(self.bus.dat_r)
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)
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fsm.act(fsm.STROBE,
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self.endpoints["data"].stb.eq(1),
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If(self.endpoints["data"].ack, fsm.next_state(fsm.IDLE))
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)
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controller = fsm.get_fragment()
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]
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return address_generator + output_buffer + controller
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return Fragment(comb, sync)
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class Writer(Actor):
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pass # TODO
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def __init__(self):
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self.bus = wishbone.Interface()
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super().__init__(
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("address_data", Sink, [("a", BV(30)), ("d", BV(32))]))
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def get_fragment(self):
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comb = [
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self.busy.eq(0),
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self.bus.we.eq(1),
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self.bus.cyc.eq(self.endpoints["address_data"].stb),
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self.bus.stb.eq(self.endpoints["address_data"].stb),
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self.bus.adr.eq(self.token("address_data").a),
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self.bus.sel.eq(0xf),
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self.bus.dat_w.eq(self.token("address_data").d),
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self.endpoints["address_data"].ack.eq(self.bus.ack)
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]
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return Fragment(comb)
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