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Merge branch 'master' of github.com:m-labs/migen

This commit is contained in:
Sebastien Bourdeauducq 2015-04-02 20:23:12 +08:00
parent ce429841d5 ce0ff1e341
commit 357c807eb1
3 changed files with 26 additions and 28 deletions
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32
migen/actorlib/spi.py
View File

@ -33,11 +33,11 @@ class SingleGenerator(Module, AutoCSR):
self.trigger = Signal() self.trigger = Signal()
trigger = self.trigger trigger = self.trigger
elif mode == MODE_SINGLE_SHOT: elif mode == MODE_SINGLE_SHOT:
self._r_shoot = CSR() self._shoot = CSR()
trigger = self._r_shoot.re trigger = self._shoot.re
elif mode == MODE_CONTINUOUS: elif mode == MODE_CONTINUOUS:
self._r_enable = CSRStorage() self._enable = CSRStorage()
trigger = self._r_enable.storage trigger = self._enable.storage
else: else:
raise ValueError raise ValueError
self.sync += If(self.source.ack | ~self.source.stb, self.source.stb.eq(trigger)) self.sync += If(self.source.ack | ~self.source.stb, self.source.stb.eq(trigger))
@ -74,10 +74,10 @@ class Collector(Module, AutoCSR):
self.busy = Signal() self.busy = Signal()
dw = sum(len(s) for s in self.sink.payload.flatten()) dw = sum(len(s) for s in self.sink.payload.flatten())
self._r_wa = CSRStorage(bits_for(depth-1), write_from_dev=True) self._wa = CSRStorage(bits_for(depth-1), write_from_dev=True)
self._r_wc = CSRStorage(bits_for(depth), write_from_dev=True, atomic_write=True) self._wc = CSRStorage(bits_for(depth), write_from_dev=True, atomic_write=True)
self._r_ra = CSRStorage(bits_for(depth-1)) self._ra = CSRStorage(bits_for(depth-1))
self._r_rd = CSRStatus(dw) self._rd = CSRStatus(dw)
### ###
@ -90,22 +90,22 @@ class Collector(Module, AutoCSR):
self.comb += [ self.comb += [
self.busy.eq(0), self.busy.eq(0),
If(self._r_wc.r != 0, If(self._wc.r != 0,
self.sink.ack.eq(1), self.sink.ack.eq(1),
If(self.sink.stb, If(self.sink.stb,
self._r_wa.we.eq(1), self._wa.we.eq(1),
self._r_wc.we.eq(1), self._wc.we.eq(1),
wp.we.eq(1) wp.we.eq(1)
) )
), ),
self._r_wa.dat_w.eq(self._r_wa.storage + 1), self._wa.dat_w.eq(self._wa.storage + 1),
self._r_wc.dat_w.eq(self._r_wc.storage - 1), self._wc.dat_w.eq(self._wc.storage - 1),
wp.adr.eq(self._r_wa.storage), wp.adr.eq(self._wa.storage),
wp.dat_w.eq(self.sink.payload.raw_bits()), wp.dat_w.eq(self.sink.payload.raw_bits()),
rp.adr.eq(self._r_ra.storage), rp.adr.eq(self._ra.storage),
self._r_rd.status.eq(rp.dat_r) self._rd.status.eq(rp.dat_r)
] ]
class _DMAController(Module): class _DMAController(Module):

2
migen/bank/description.py
View File

@ -8,8 +8,6 @@ class _CSRBase(HUID):
self.name = get_obj_var_name(name) self.name = get_obj_var_name(name)
if self.name is None: if self.name is None:
raise ValueError("Cannot extract CSR name from code, need to specify.") raise ValueError("Cannot extract CSR name from code, need to specify.")
if len(self.name) > 2 and self.name[:2] == "r_":
self.name = self.name[2:]
self.size = size self.size = size
class CSR(_CSRBase): class CSR(_CSRBase):

20
migen/flow/isd.py
View File

@ -45,11 +45,11 @@ class EndpointReporter(Module, AutoCSR):
class DFGReporter(DFGHook, AutoCSR): class DFGReporter(DFGHook, AutoCSR):
def __init__(self, dfg, nbits): def __init__(self, dfg, nbits):
self._r_magic = CSRStatus(16) self._magic = CSRStatus(16)
self._r_neps = CSRStatus(8) self._neps = CSRStatus(8)
self._r_nbits = CSRStatus(8) self._nbits = CSRStatus(8)
self._r_freeze = CSRStorage() self._freeze = CSRStorage()
self._r_reset = CSR() self._reset = CSR()
### ###
@ -58,12 +58,12 @@ class DFGReporter(DFGHook, AutoCSR):
hooks = list(self.hooks_iter()) hooks = list(self.hooks_iter())
self.comb += [ self.comb += [
self._r_magic.status.eq(ISD_MAGIC), self._magic.status.eq(ISD_MAGIC),
self._r_neps.status.eq(len(hooks)), self._neps.status.eq(len(hooks)),
self._r_nbits.status.eq(nbits) self._nbits.status.eq(nbits)
] ]
for h in hooks: for h in hooks:
self.comb += [ self.comb += [
h.freeze.eq(self._r_freeze.storage), h.freeze.eq(self._freeze.storage),
h.reset.eq(self._r_reset.re) h.reset.eq(self._reset.re)
] ]