soc/cores: Add simple VideoOut core with VideoTimingGenerator, Video Patterns, VideoTerminal, VideoDVIPHY and VideoVGAPHY.
This commit is contained in:
Florent Kermarrec
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c5ee6741a0
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import math
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from migen import *
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from migen.genlib.cdc import MultiReg
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import stream
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# Video Constants ----------------------------------------------------------------------------------
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hbits = 12
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vbits = 12
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# Video Timings ------------------------------------------------------------------------------------
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video_timings = {
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"640x480@75Hz" : {
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"pix_clk" : 31.5e6,
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"h_active" : 640,
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"h_blanking" : 200,
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"h_sync_offset" : 16,
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"h_sync_width" : 64,
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"v_active" : 480,
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"v_blanking" : 20,
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"v_sync_offset" : 1,
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"v_sync_width" : 3,
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},
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"800x600@60Hz" : {
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"pix_clk" : 40e6,
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"h_active" : 800,
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"h_blanking" : 256,
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"h_sync_offset" : 40,
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"h_sync_width" : 128,
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"v_active" : 600,
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"v_blanking" : 28,
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"v_sync_offset" : 1,
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"v_sync_width" : 4,
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},
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"800x600@75Hz": {
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"pix_clk" : 49.5e6,
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"h_active" : 800,
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"h_blanking" : 256,
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"h_sync_offset" : 16,
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"h_sync_width" : 80,
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"v_active" : 600,
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"v_blanking" : 25,
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"v_sync_offset" : 1,
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"v_sync_width" : 3,
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},
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"1024x768@60Hz": {
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"pix_clk" : 65e6,
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"h_active" : 1024,
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"h_blanking" : 320,
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"h_sync_offset" : 24,
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"h_sync_width" : 136,
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"v_active" : 768,
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"v_blanking" : 38,
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"v_sync_offset" : 3,
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"v_sync_width" : 6,
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},
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"1024x768@75Hz": {
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"pix_clk" : 78.8e6,
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"h_active" : 1024,
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"h_blanking" : 288,
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"h_sync_offset" : 16,
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"h_sync_width" : 96,
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"v_active" : 768,
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"v_blanking" : 32,
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"v_sync_offset" : 1,
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"v_sync_width" : 3,
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},
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"1280x720@60Hz": {
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"pix_clk" : 74.25e6,
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"h_active" : 1280,
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"h_blanking" : 370,
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"h_sync_offset" : 220,
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"h_sync_width" : 40,
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"v_active" : 720,
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"v_blanking" : 30,
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"v_sync_offset" : 5,
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"v_sync_width" : 5,
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},
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"1920x1080@30Hz": {
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"pix_clk" : 89.01e6,
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"h_active" : 1920,
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"h_blanking" : 720,
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"h_sync_offset" : 528,
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"h_sync_width" : 44,
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"v_active" : 1080,
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"v_blanking" : 45,
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"v_sync_offset" : 4,
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"v_sync_width" : 5,
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},
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"1920x1080@60Hz": {
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"pix_clk" : 148.35e6,
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"h_active" : 1920,
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"h_blanking" : 280,
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"h_sync_offset" : 88,
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"h_sync_width" : 44,
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"v_active" : 1080,
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"v_blanking" : 45,
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"v_sync_offset" : 4,
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"v_sync_width" : 5,
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},
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}
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# Video Timing Generator ---------------------------------------------------------------------------
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video_timing_layout = [
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# Synchronization signals.
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("hsync", 1),
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("vsync", 1),
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("de", 1),
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# Extended/Optional synchronization signals.
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("hres", hbits),
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("vres", vbits),
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("hcount", hbits),
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("vcount", vbits),
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]
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video_data_layout = [
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# Synchronization signals.
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("hsync", 1),
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("vsync", 1),
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("de", 1),
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# Data signals.
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("r", 8),
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("g", 8),
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("b", 8),
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]
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class VideoTimingGenerator(Module, AutoCSR):
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def __init__(self, default_video_timings="800x600@60Hz"):
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vt = video_timings[default_video_timings]
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# MMAP Control/Status Registers.
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self._enable = CSRStorage(reset=1)
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self._hres = CSRStorage(hbits, vt["h_active"])
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self._hsync_start = CSRStorage(hbits, vt["h_active"] + vt["h_sync_offset"])
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self._hsync_end = CSRStorage(hbits, vt["h_active"] + vt["h_sync_offset"] + vt["h_sync_width"])
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self._hscan = CSRStorage(hbits, vt["h_active"] + vt["h_blanking"])
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self._vres = CSRStorage(vbits, vt["v_active"])
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self._vsync_start = CSRStorage(vbits, vt["v_active"] + vt["v_sync_offset"])
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self._vsync_end = CSRStorage(vbits, vt["v_active"] + vt["v_sync_offset"] + vt["v_sync_width"])
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self._vscan = CSRStorage(vbits, vt["v_active"] + vt["v_blanking"])
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# Video Timing Source
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self.source = source = stream.Endpoint(video_timing_layout)
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# # #
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# Resynchronize Enable to Video clock domain.
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self.enable = enable = Signal()
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self.specials += MultiReg(self._enable.storage, enable)
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# Resynchronize Horizontal Timings to Video clock domain.
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self.hres = hres = Signal(hbits)
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self.hsync_start = hsync_start = Signal(hbits)
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self.hsync_end = hsync_end = Signal(hbits)
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self.hscan = hscan = Signal(hbits)
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self.specials += MultiReg(self._hres.storage, hres)
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self.specials += MultiReg(self._hsync_start.storage, hsync_start)
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self.specials += MultiReg(self._hsync_end.storage, hsync_end)
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self.specials += MultiReg(self._hscan.storage, hscan)
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# Resynchronize Vertical Timings to Video clock domain.
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self.vres = vres = Signal(vbits)
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self.vsync_start = vsync_start = Signal(vbits)
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self.vsync_end = vsync_end = Signal(vbits)
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self.vscan = vscan = Signal(vbits)
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self.specials += MultiReg(self._vres.storage, vres)
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self.specials += MultiReg(self._vsync_start.storage, vsync_start)
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self.specials += MultiReg(self._vsync_end.storage, vsync_end)
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self.specials += MultiReg(self._vscan.storage, vscan)
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# Generate timings.
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hactive = Signal()
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vactive = Signal()
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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NextValue(hactive, 0),
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NextValue(vactive, 0),
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NextValue(source.hres, hres),
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NextValue(source.vres, vres),
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NextValue(source.hcount, 0),
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NextValue(source.vcount, 0),
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If(enable,
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NextState("RUN")
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)
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)
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self.comb += source.de.eq(hactive & vactive) # DE when both HActive and VActive.
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self.sync += source.first.eq((source.hcount == 0) & (source.vcount == 0)),
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self.sync += source.last.eq( (source.hcount == hscan) & (source.vcount == vscan)),
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fsm.act("RUN",
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source.valid.eq(1),
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If(source.ready,
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# Increment HCount.
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NextValue(source.hcount, source.hcount + 1),
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# Generate HActive / HSync.
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If(source.hcount == 0, NextValue(hactive, 1)), # Start of HActive.
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If(source.hcount == hres, NextValue(hactive, 0)), # End of HActive.
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If(source.hcount == hsync_start, NextValue(source.hsync, 1)), # Start of HSync.
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If(source.hcount == hsync_end, NextValue(source.hsync, 0)), # End of HSync.
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# End of HScan.
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If(source.hcount == hscan,
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# Reset HCount.
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NextValue(source.hcount, 0),
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# Increment VCount.
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NextValue(source.vcount, source.vcount + 1),
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# Generate VActive / VSync.
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If(source.vcount == 0, NextValue(vactive, 1)), # Start of VActive.
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If(source.vcount == vres, NextValue(vactive, 0)), # End of HActive.
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If(source.vcount == vsync_start, NextValue(source.vsync, 1)), # Start of VSync.
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If(source.vcount == vsync_end, NextValue(source.vsync, 0)), # End of VSync.
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# End of VScan.
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If(source.vcount == vscan,
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# Reset VCount.
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NextValue(source.vcount, 0),
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)
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)
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)
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)
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# Patterns -----------------------------------------------------------------------------------------
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class ColorBarsPattern(Module):
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"""Color Bars Pattern"""
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def __init__(self):
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self.enable = Signal(reset=1)
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self.vtg_sink = vtg_sink = stream.Endpoint(video_timing_layout)
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self.source = source = stream.Endpoint(video_data_layout)
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# # #
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enable = Signal()
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self.specials += MultiReg(self.enable, enable)
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# Control Path.
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pix = Signal(hbits)
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bar = Signal(3)
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fsm = FSM(reset_state="IDLE")
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fsm = ResetInserter()(fsm)
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self.submodules.fsm = fsm
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self.comb += fsm.reset.eq(~self.enable)
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fsm.act("IDLE",
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NextValue(pix, 0),
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NextValue(bar, 0),
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vtg_sink.ready.eq(1),
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If(vtg_sink.valid & vtg_sink.first & (vtg_sink.hcount == 0) & (vtg_sink.vcount == 0),
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vtg_sink.ready.eq(0),
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NextState("RUN")
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)
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)
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fsm.act("RUN",
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vtg_sink.connect(source, keep={"valid", "ready", "last", "de", "hsync", "vsync"}),
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If(source.valid & source.ready & source.de,
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NextValue(pix, pix + 1),
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If(pix == (vtg_sink.hres[3:] -1), # 8 Color Bars.
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NextValue(pix, 0),
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NextValue(bar, bar + 1)
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)
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)
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)
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# Data Path.
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color_bar = [
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# R G B
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[0xff, 0xff, 0xff], # White
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[0xff, 0xff, 0x00], # Yellow
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[0x00, 0xff, 0xff], # Cyan
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[0x00, 0xff, 0x00], # Green
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[0xff, 0x00, 0xff], # Purple
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[0xff, 0x00, 0x00], # Red
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[0x00, 0x00, 0xff], # Blue
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[0x00, 0x00, 0x00], # Black
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]
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cases = {}
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for i in range(8):
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cases[i] = [
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source.r.eq(color_bar[i][0]),
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source.g.eq(color_bar[i][1]),
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source.b.eq(color_bar[i][2])
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]
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self.comb += Case(bar, cases)
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# Video Terminal -----------------------------------------------------------------------------------
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def import_bdf_font(filename):
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import csv
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font = [0]*16*256
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with open(filename) as f:
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reader = csv.reader(f, delimiter=" ")
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char = None
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bitmap_enable = False
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bitmap_index = 0
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for l in reader:
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if l[0] == "ENCODING":
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char = int(l[1], 0)
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if l[0] == "ENDCHAR":
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bitmap_enable = False
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if bitmap_enable:
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if char < 256:
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font[char*16 + bitmap_index] = int("0x"+l[0], 0)
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bitmap_index += 1
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if l[0] == "BITMAP":
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bitmap_enable = True
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bitmap_index = 0
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return font
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class CSIInterpreter(Module):
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# FIXME: Very basic/minimal implementation for now.
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esc_start = 0x1b
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csi_start = ord("[")
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csi_param_min = 0x30
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csi_param_max = 0x3f
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def __init__(self):
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self.sink = sink = stream.Endpoint([("data", 8)])
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self.source = source = stream.Endpoint([("data", 8)])
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self.color = Record([("r", 8), ("g", 8), ("b", 8)])
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self.color.r.reset = 0xff
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self.color.g.reset = 0xff
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self.color.b.reset = 0xff
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# # #
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csi_count = Signal(3)
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csi_bytes = Array([Signal(8) for _ in range(8)])
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csi_final = Signal(8)
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self.submodules.fsm = fsm = FSM(reset_state="RECOPY")
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fsm.act("RECOPY",
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sink.connect(source),
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If(sink.valid & (sink.data == self.esc_start),
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source.valid.eq(0),
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sink.ready.eq(1),
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NextState("GET-CSI-START")
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)
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)
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fsm.act("GET-CSI-START",
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sink.ready.eq(1),
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If(sink.valid,
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If(sink.data == self.csi_start,
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NextValue(csi_count, 0),
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NextState("GET-CSI-PARAMETERS")
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).Else(
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NextState("RECOPY")
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)
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)
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)
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fsm.act("GET-CSI-PARAMETERS",
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If(sink.valid,
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If((sink.data >= self.csi_param_min) & (sink.data <= self.csi_param_max),
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sink.ready.eq(1),
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NextValue(csi_count, csi_count + 1),
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NextValue(csi_bytes[csi_count], sink.data),
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).Else(
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||||||
|
NextState("GET-CSI-FINAL")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
fsm.act("GET-CSI-FINAL",
|
||||||
|
sink.ready.eq(1),
|
||||||
|
NextValue(csi_final, sink.data),
|
||||||
|
NextState("DECODE-CSI")
|
||||||
|
)
|
||||||
|
fsm.act("DECODE-CSI",
|
||||||
|
If(csi_final == ord("m"),
|
||||||
|
# FIXME: Write color in Terminal Mem.
|
||||||
|
If((csi_bytes[0] == ord("9")) and (csi_bytes[1] == ord("2")),
|
||||||
|
NextValue(self.color.r, 0x89),
|
||||||
|
NextValue(self.color.g, 0xe2),
|
||||||
|
NextValue(self.color.b, 0x34),
|
||||||
|
).Else(
|
||||||
|
NextValue(self.color.r, self.color.r.reset),
|
||||||
|
NextValue(self.color.g, self.color.g.reset),
|
||||||
|
NextValue(self.color.b, self.color.b.reset),
|
||||||
|
),
|
||||||
|
),
|
||||||
|
NextState("RECOPY")
|
||||||
|
)
|
||||||
|
|
||||||
|
class VideoTerminal(Module):
|
||||||
|
def __init__(self, hres=640, vres=480, with_csi_interpreter=True):
|
||||||
|
self.enable = Signal(reset=1)
|
||||||
|
self.vtg_sink = vtg_sink = stream.Endpoint(video_timing_layout)
|
||||||
|
self.uart_sink = uart_sink = stream.Endpoint([("data", 8)])
|
||||||
|
self.source = source = stream.Endpoint(video_data_layout)
|
||||||
|
|
||||||
|
# # #
|
||||||
|
|
||||||
|
# Font Mem.
|
||||||
|
# ---------
|
||||||
|
os.system("wget https://github.com/enjoy-digital/litex/files/6076336/ter-u16b.txt") # FIXME: Store Font in LiteX?
|
||||||
|
os.system("mv ter-u16b.txt ter-u16b.bdf")
|
||||||
|
font = import_bdf_font("ter-u16b.bdf")
|
||||||
|
font_width = 8
|
||||||
|
font_heigth = 16
|
||||||
|
font_mem = Memory(width=8, depth=4096, init=font)
|
||||||
|
font_rdport = font_mem.get_port(write_capable=False, has_re=True)
|
||||||
|
self.specials += font_mem, font_rdport
|
||||||
|
|
||||||
|
# Terminal Mem.
|
||||||
|
# -------------
|
||||||
|
term_colums = 128 # 80 rounded to next power of two.
|
||||||
|
term_lines = math.floor(vres/font_heigth)
|
||||||
|
term_depth = term_colums * term_lines
|
||||||
|
term_init = [ord(c) for c in [" "]*term_colums*term_lines]
|
||||||
|
term_mem = Memory(width=font_width, depth=term_depth, init=term_init)
|
||||||
|
term_wrport = term_mem.get_port(write_capable=True)
|
||||||
|
term_rdport = term_mem.get_port(write_capable=False, has_re=True)
|
||||||
|
self.specials += term_mem, term_wrport, term_rdport
|
||||||
|
|
||||||
|
# UART Terminal Fill.
|
||||||
|
# -------------------
|
||||||
|
|
||||||
|
# Optional CSI Interpreter.
|
||||||
|
if with_csi_interpreter:
|
||||||
|
self.submodules.csi_interpreter = CSIInterpreter()
|
||||||
|
self.comb += uart_sink.connect(self.csi_interpreter.sink)
|
||||||
|
uart_sink = self.csi_interpreter.source
|
||||||
|
|
||||||
|
self.submodules.uart_fifo = stream.SyncFIFO([("data", 8)], 8)
|
||||||
|
self.comb += uart_sink.connect(self.uart_fifo.sink)
|
||||||
|
uart_sink = self.uart_fifo.source
|
||||||
|
|
||||||
|
# UART Reception and Terminal Fill.
|
||||||
|
x_term = term_wrport.adr[:7]
|
||||||
|
y_term = term_wrport.adr[7:]
|
||||||
|
y_term_rollover = Signal()
|
||||||
|
self.submodules.uart_fsm = uart_fsm = FSM(reset_state="IDLE")
|
||||||
|
uart_fsm.act("IDLE",
|
||||||
|
If(uart_sink.valid,
|
||||||
|
If(uart_sink.data == ord("\n"),
|
||||||
|
uart_sink.ready.eq(1), # Ack sink.
|
||||||
|
NextState("INCR-Y")
|
||||||
|
).Elif(uart_sink.data == ord("\r"),
|
||||||
|
uart_sink.ready.eq(1), # Ack sink.
|
||||||
|
NextState("RST-X")
|
||||||
|
).Else(
|
||||||
|
NextState("WRITE")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
uart_fsm.act("WRITE",
|
||||||
|
uart_sink.ready.eq(1),
|
||||||
|
term_wrport.we.eq(1),
|
||||||
|
term_wrport.dat_w.eq(uart_sink.data),
|
||||||
|
NextState("INCR-X")
|
||||||
|
)
|
||||||
|
uart_fsm.act("RST-X",
|
||||||
|
NextValue(x_term, 0),
|
||||||
|
NextState("IDLE")
|
||||||
|
)
|
||||||
|
uart_fsm.act("INCR-X",
|
||||||
|
NextValue(x_term, x_term + 1),
|
||||||
|
NextState("IDLE"),
|
||||||
|
If(x_term == (80 - 1),
|
||||||
|
NextValue(x_term, 0),
|
||||||
|
NextState("INCR-Y")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
uart_fsm.act("RST-Y",
|
||||||
|
NextValue(y_term, 0),
|
||||||
|
NextState("CLEAR-X")
|
||||||
|
)
|
||||||
|
uart_fsm.act("INCR-Y",
|
||||||
|
NextValue(y_term, y_term + 1),
|
||||||
|
NextState("CLEAR-X"),
|
||||||
|
If(y_term == (term_lines - 1),
|
||||||
|
NextValue(y_term_rollover, 1),
|
||||||
|
NextState("RST-Y")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
uart_fsm.act("CLEAR-X",
|
||||||
|
NextValue(x_term, x_term + 1),
|
||||||
|
term_wrport.we.eq(1),
|
||||||
|
term_wrport.dat_w.eq(ord(" ")),
|
||||||
|
If(x_term == (80 - 1),
|
||||||
|
NextValue(x_term, 0),
|
||||||
|
NextState("IDLE")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
# Video Generation.
|
||||||
|
# -----------------
|
||||||
|
ce = (vtg_sink.valid & vtg_sink.ready)
|
||||||
|
|
||||||
|
# Timing delay line.
|
||||||
|
latency = 2
|
||||||
|
timing_bufs = [stream.Buffer(video_timing_layout) for i in range(latency)]
|
||||||
|
self.comb += vtg_sink.connect(timing_bufs[0].sink)
|
||||||
|
for i in range(len(timing_bufs) - 1):
|
||||||
|
self.comb += timing_bufs[i].source.connect(timing_bufs[i+1].sink)
|
||||||
|
self.comb += timing_bufs[-1].source.connect(source, keep={"valid", "ready", "last", "de", "hsync", "vsync"})
|
||||||
|
self.submodules += timing_bufs
|
||||||
|
|
||||||
|
# Compute X/Y position.
|
||||||
|
x = vtg_sink.hcount[int(math.log2(font_width)):]
|
||||||
|
y = vtg_sink.vcount[int(math.log2(font_heigth)):]
|
||||||
|
y_rollover = Signal(8)
|
||||||
|
self.comb += [
|
||||||
|
If(~y_term_rollover,
|
||||||
|
y_rollover.eq(y)
|
||||||
|
).Else(
|
||||||
|
# FIXME: Use Modulo.
|
||||||
|
If((y + y_term + 1) >= term_lines,
|
||||||
|
y_rollover.eq(y + y_term + 1 - term_lines)
|
||||||
|
).Else(
|
||||||
|
y_rollover.eq(y + y_term + 1)
|
||||||
|
),
|
||||||
|
)
|
||||||
|
]
|
||||||
|
|
||||||
|
# Get character from Terminal Mem.
|
||||||
|
term_dat_r = Signal(font_width)
|
||||||
|
self.comb += term_rdport.re.eq(ce)
|
||||||
|
self.comb += term_rdport.adr.eq(x + y_rollover*term_colums)
|
||||||
|
self.comb += [
|
||||||
|
term_dat_r.eq(term_rdport.dat_r),
|
||||||
|
If((x >= 80) | (y >= term_lines),
|
||||||
|
term_dat_r.eq(ord(" ")), # Out of range, generate space.
|
||||||
|
)
|
||||||
|
]
|
||||||
|
|
||||||
|
# Translate character to video data through Font Mem.
|
||||||
|
self.comb += font_rdport.re.eq(ce)
|
||||||
|
self.comb += font_rdport.adr.eq(term_dat_r*font_heigth + timing_bufs[0].source.vcount[:4])
|
||||||
|
bit = Signal()
|
||||||
|
cases = {}
|
||||||
|
for i in range(font_width):
|
||||||
|
cases[i] = [bit.eq(font_rdport.dat_r[font_width-1-i])]
|
||||||
|
self.comb += Case(timing_bufs[1].source.hcount[:int(math.log2(font_width))], cases)
|
||||||
|
# FIXME: Allow static/dynamic Font color.
|
||||||
|
self.comb += If(bit,
|
||||||
|
source.r.eq(0xff),
|
||||||
|
source.g.eq(0xff),
|
||||||
|
source.b.eq(0xff),
|
||||||
|
).Else(
|
||||||
|
source.r.eq(0x00),
|
||||||
|
source.g.eq(0x00),
|
||||||
|
source.b.eq(0x00)
|
||||||
|
)
|
||||||
|
|
||||||
|
# Video PHYs ---------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
class VideoDVIPHY(Module):
|
||||||
|
def __init__(self, pads, clock_domain="sys"):
|
||||||
|
self.sink = sink = stream.Endpoint(video_data_layout)
|
||||||
|
|
||||||
|
# # #
|
||||||
|
|
||||||
|
# FIXME: Use IOs primitives.
|
||||||
|
|
||||||
|
self.comb += [
|
||||||
|
# Always ack Sink, no backpressure.
|
||||||
|
sink.ready.eq(1),
|
||||||
|
|
||||||
|
# Drive DVI Clk.
|
||||||
|
pads.clk.eq(ClockSignal(clock_domain)),
|
||||||
|
|
||||||
|
# Drive DVI Controls.
|
||||||
|
pads.de.eq(sink.de),
|
||||||
|
pads.hsync.eq(sink.hsync),
|
||||||
|
pads.vsync.eq(sink.vsync),
|
||||||
|
|
||||||
|
# Drive DVI Datas.
|
||||||
|
pads.r.eq(sink.r[8-len(pads.r):]),
|
||||||
|
pads.g.eq(sink.g[8-len(pads.g):]),
|
||||||
|
pads.b.eq(sink.b[8-len(pads.b):]),
|
||||||
|
]
|
||||||
|
|
||||||
|
|
||||||
|
class VideoVGAPHY(Module):
|
||||||
|
def __init__(self, pads, clock_domain="sys"):
|
||||||
|
self.sink = sink = stream.Endpoint(video_data_layout)
|
||||||
|
|
||||||
|
# # #
|
||||||
|
|
||||||
|
# FIXME: Use IOs primitives.
|
||||||
|
|
||||||
|
self.comb += [
|
||||||
|
# Always ack Sink, no backpressure.
|
||||||
|
sink.ready.eq(1),
|
||||||
|
|
||||||
|
# Drive DVI Controls.
|
||||||
|
pads.hsync_n.eq(~sink.hsync),
|
||||||
|
pads.vsync_n.eq(~sink.vsync),
|
||||||
|
|
||||||
|
# Drive DVI Datas.
|
||||||
|
pads.r.eq(sink.r[8-len(pads.r):]),
|
||||||
|
pads.g.eq(sink.g[8-len(pads.g):]),
|
||||||
|
pads.b.eq(sink.b[8-len(pads.b):]),
|
||||||
|
]
|
||||||
Loading…
Reference in New Issue