Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal

This commit is contained in:
Florent Kermarrec 2019-11-20 19:24:40 +01:00
parent e8e70b164a
commit 36107cdfd7
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex/soc/cores/clock.py
View File

@ -225,7 +225,7 @@ class S7PLL(XilinxClocking):
config = self.compute_config()
pll_fb = Signal()
self.params.update(
p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked,
p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
@ -319,7 +319,7 @@ class USPLL(XilinxClocking):
config = self.compute_config()
pll_fb = Signal()
self.params.update(
p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked,
p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
@ -355,7 +355,7 @@ class USMMCM(XilinxClocking):
config = self.compute_config()
mmcm_fb = Signal()
self.params.update(
p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked,
p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,