soc/integration: use AXILiteSRAM when using bus_standard="axi-lite"

This commit is contained in:
Jędrzej Boczar 2020-07-22 16:57:51 +02:00
parent 8ae501c391
commit 367eb12240
1 changed files with 10 additions and 2 deletions

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@ -766,8 +766,16 @@ class SoC(Module):
self.csr.add(name, use_loc_if_exists=True) self.csr.add(name, use_loc_if_exists=True)
def add_ram(self, name, origin, size, contents=[], mode="rw"): def add_ram(self, name, origin, size, contents=[], mode="rw"):
ram_bus = wishbone.Interface(data_width=self.bus.data_width) ram_cls = {
ram = wishbone.SRAM(size, bus=ram_bus, init=contents, read_only=(mode == "r")) "wishbone": wishbone.SRAM,
"axi-lite": axi.AXILiteSRAM,
}[self.bus.standard]
interface_cls = {
"wishbone": wishbone.Interface,
"axi-lite": axi.AXILiteInterface,
}[self.bus.standard]
ram_bus = interface_cls(data_width=self.bus.data_width)
ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"))
self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode)) self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
self.check_if_exists(name) self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format( self.logger.info("RAM {} {} {}.".format(