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soc: simplify integrated memory parameters

This commit is contained in:
Sebastien Bourdeauducq 2015-04-02 00:09:38 +08:00
parent 273242b399
commit 369086a178
11 changed files with 48 additions and 70 deletions
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6
make.py
View File

@ -125,9 +125,9 @@ CPU type: {}
actions["build-bios"] = True
if not actions["load-bitstream"]:
actions["flash-bitstream"] = True
if not soc.with_integrated_rom:
if not soc.integrated_rom_size:
actions["flash-bios"] = True
if actions["build-bitstream"] and soc.with_integrated_rom:
if actions["build-bitstream"] and soc.integrated_rom_size:
actions["build-bios"] = True
if actions["build-bios"]:
actions["build-headers"] = True
@ -176,7 +176,7 @@ CPU type: {}
raise OSError("BIOS build failed")
if actions["build-bitstream"]:
if soc.with_integrated_rom:
if soc.integrated_rom_size:
with open(bios_file, "rb") as boot_file:
boot_data = []
while True:

42
misoclib/soc/__init__.py
View File

@ -34,9 +34,9 @@ class SoC(Module):
}
def __init__(self, platform, clk_freq,
cpu_type="lm32", cpu_reset_address=0x00000000,
with_integrated_rom=False, rom_size=0x8000,
with_integrated_sram=True, sram_size=4096,
with_integrated_main_ram=False, main_ram_size=64*1024,
integrated_rom_size=0,
integrated_sram_size=4096,
integrated_main_ram_size=0,
with_csr=True, csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200,
with_identifier=True,
@ -45,19 +45,13 @@ class SoC(Module):
self.clk_freq = clk_freq
self.cpu_type = cpu_type
if with_integrated_rom:
self.cpu_reset_address = 0
else:
self.cpu_reset_address = cpu_reset_address
if integrated_rom_size:
cpu_reset_address = 0
self.cpu_reset_address = cpu_reset_address
self.with_integrated_rom = with_integrated_rom
self.rom_size = rom_size
self.with_integrated_sram = with_integrated_sram
self.sram_size = sram_size
self.with_integrated_main_ram = with_integrated_main_ram
self.main_ram_size = main_ram_size
self.integrated_rom_size = integrated_rom_size
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
@ -84,18 +78,18 @@ class SoC(Module):
self.add_wb_master(self.cpu_or_bridge.ibus)
self.add_wb_master(self.cpu_or_bridge.dbus)
if with_integrated_rom:
self.submodules.rom = wishbone.SRAM(rom_size, read_only=True)
self.register_rom(self.rom.bus, rom_size)
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True)
self.register_rom(self.rom.bus, integrated_rom_size)
if with_integrated_sram:
self.submodules.sram = wishbone.SRAM(sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus, sram_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if with_integrated_main_ram:
self.submodules.main_ram = wishbone.SRAM(main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, main_ram_size)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
if with_csr:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(csr_data_width, csr_address_width))

2
misoclib/soc/sdram.py
View File

@ -78,7 +78,7 @@ class SDRAMSoC(SoC):
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
def do_finalize(self):
if not self.with_integrated_main_ram:
if not self.integrated_ram_size:
if not self._sdram_phy_registered:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
SoC.do_finalize(self)

8
targets/de0nano.py
View File

@ -1,12 +1,8 @@
from migen.fhdl.std import *
from migen.bus import wishbone
from misoclib.cpu.peripherals import gpio
from misoclib.mem import sdram
from misoclib.mem.sdram.module import IS42S16160
from misoclib.mem.sdram.phy import gensdrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
from misoclib.com import uart
from misoclib.soc.sdram import SDRAMSoC
class _PLL(Module):
@ -86,13 +82,13 @@ class BaseSoC(SDRAMSoC):
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
clk_freq=100*1000000,
with_integrated_rom=True,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), IS42S16160(self.clk_freq))
self.register_sdram_phy(self.sdrphy)

21
targets/kc705.py
View File

@ -1,7 +1,6 @@
from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoclib.mem import sdram
from misoclib.mem.sdram.module import MT8JTF12864
from misoclib.mem.sdram.phy import k7ddrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
@ -85,20 +84,18 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform)
if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), MT8JTF12864(self.clk_freq))
self.register_sdram_phy(self.ddrphy)
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.flash_boot_address = 0xb00000
# If not in ROM, BIOS is in SPI flash
if not self.with_integrated_rom:
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)
class MiniSoC(BaseSoC):

6
targets/minispartan6.py
View File

@ -3,11 +3,9 @@ from fractions import Fraction
from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoclib.mem import sdram
from misoclib.mem.sdram.module import AS4C16M16
from misoclib.mem.sdram.phy import gensdrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
from misoclib.mem.flash import spiflash
from misoclib.soc.sdram import SDRAMSoC
class _CRG(Module):
@ -66,13 +64,13 @@ class BaseSoC(SDRAMSoC):
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 80*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
with_integrated_rom=True,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), AS4C16M16(clk_freq))
self.register_sdram_phy(self.sdrphy)

4
targets/mlabs_video.py
View File

@ -44,7 +44,7 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46V32M16(self.clk_freq),
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy)
@ -53,7 +53,7 @@ class BaseSoC(SDRAMSoC):
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
]
if not self.with_integrated_rom:
if not self.integrated_rom_size:
clk_period_ns = 1000000000/self.clk_freq
self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
ceil(110/clk_period_ns), ceil(50/clk_period_ns))

12
targets/pipistrello.py
View File

@ -3,7 +3,6 @@ from fractions import Fraction
from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoclib.mem import sdram
from misoclib.mem.sdram.module import MT46H32M16
from misoclib.mem.sdram.phy import s6ddrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
@ -97,8 +96,6 @@ class BaseSoC(SDRAMSoC):
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 75*1000000
if not kwargs.get("with_integrated_rom"):
kwargs["rom_size"] = 0x1000000 # 128 Mb
SDRAMSoC.__init__(self, platform, clk_freq,
cpu_reset_address=0x170000, # 1.5 MB
sdram_controller_settings=sdram_controller_settings,
@ -106,7 +103,7 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq)
if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46H32M16(self.clk_freq),
rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
self.comb += [
@ -118,10 +115,9 @@ class BaseSoC(SDRAMSoC):
""")
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
# If not in ROM, BIOS is in SPI flash
if not self.with_integrated_rom:
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus)
self.register_rom(self.spiflash.bus, 0x1000000)
default_subtarget = BaseSoC

11
targets/ppro.py
View File

@ -3,7 +3,6 @@ from fractions import Fraction
from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoclib.mem import sdram
from misoclib.mem.sdram.module import MT48LC4M16
from misoclib.mem.sdram.phy import gensdrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
@ -77,15 +76,13 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq)
if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), MT48LC4M16(clk_freq))
self.register_sdram_phy(self.sdrphy)
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000
# If not in ROM, BIOS is in SPI flash
if not self.with_integrated_rom:
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)
default_subtarget = BaseSoC

4
targets/simple.py
View File

@ -10,8 +10,8 @@ class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
with_integrated_rom=True,
with_integrated_main_ram=True, main_ram_size=16*1024,
integrated_rom_size=0x8000,
integrated_main_ram_size=16*1024,
**kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))

2
targets/versa.py
View File

@ -9,7 +9,7 @@ class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=100*1000000,
with_integrated_rom=True,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
self.comb += platform.request("user_led", 0).eq(ResetSignal())