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build/altera/common: improve presentation

This commit is contained in:
Florent Kermarrec 2019-08-08 16:02:34 +02:00
parent 95953d2928
commit 36d9d78c5e
1 changed files with 28 additions and 16 deletions
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44
litex/build/altera/common.py
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@ -12,11 +12,14 @@ from migen.fhdl.structure import *
class AlteraDifferentialInputImpl(Module): class AlteraDifferentialInputImpl(Module):
def __init__(self, i_p, i_n, o): def __init__(self, i_p, i_n, o):
self.specials += Instance("ALT_INBUF_DIFF", self.specials += [
name="ibuf_diff", Instance("ALT_INBUF_DIFF",
i_i=i_p, name="ibuf_diff",
i_ibar=i_n, i_i=i_p,
o_o=o) i_ibar=i_n,
o_o=o
)
]
class AlteraDifferentialInput: class AlteraDifferentialInput:
@ -27,11 +30,14 @@ class AlteraDifferentialInput:
class AlteraDifferentialOutputImpl(Module): class AlteraDifferentialOutputImpl(Module):
def __init__(self, i, o_p, o_n): def __init__(self, i, o_p, o_n):
self.specials += Instance("ALT_OUTBUF_DIFF", self.specials += [
name="obuf_diff", Instance("ALT_OUTBUF_DIFF",
i_i=i, name="obuf_diff",
o_o=o_p, i_i=i,
o_obar=o_n) o_o=o_p,
o_obar=o_n
)
]
class AlteraDifferentialOutput: class AlteraDifferentialOutput:
@ -39,6 +45,7 @@ class AlteraDifferentialOutput:
def lower(dr): def lower(dr):
return AlteraDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) return AlteraDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
class AlteraAsyncResetSynchronizerImpl(Module): class AlteraAsyncResetSynchronizerImpl(Module):
def __init__(self, cd, async_reset): def __init__(self, cd, async_reset):
if not hasattr(async_reset, "attr"): if not hasattr(async_reset, "attr"):
@ -46,14 +53,19 @@ class AlteraAsyncResetSynchronizerImpl(Module):
self.comb += async_reset.eq(i) self.comb += async_reset.eq(i)
rst_meta = Signal() rst_meta = Signal()
self.specials += [ self.specials += [
Instance("DFF", i_d=0, i_clk=cd.clk, i_clrn=1, Instance("DFF",
i_prn=async_reset, o_q=rst_meta, i_d=0, i_clk=cd.clk, i_clrn=1,
attr={"async_reg", "ars_ff1"}), i_prn=async_reset, o_q=rst_meta,
Instance("DFF", i_d=rst_meta, i_clk=cd.clk, i_clrn=1, attr={"async_reg", "ars_ff1"}
i_prn=async_reset, o_q=cd.rst, ),
attr={"async_reg", "ars_ff2"}) Instance("DFF",
i_d=rst_meta, i_clk=cd.clk, i_clrn=1,
i_prn=async_reset, o_q=cd.rst,
attr={"async_reg", "ars_ff2"}
)
] ]
class AlteraAsyncResetSynchronizer: class AlteraAsyncResetSynchronizer:
@staticmethod @staticmethod
def lower(dr): def lower(dr):