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Change SocRegion readonly definition 

From (mode == "r") to ("w" not in mode).
This allows to have more possible modes than r & w.
This commit is contained in:
Christian Klarhorst 2022-08-30 15:47:59 +02:00
parent 91a115584f
commit 37360587e3
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc.py
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@ -883,7 +883,7 @@ class SoC(Module):
"axi" : axi.AXILiteInterface, # FIXME: Use AXI-Lite for now, create AXISRAM. "axi" : axi.AXILiteInterface, # FIXME: Use AXI-Lite for now, create AXISRAM.
}[self.bus.standard] }[self.bus.standard]
ram_bus = interface_cls(data_width=self.bus.data_width, bursting=self.bus.bursting) ram_bus = interface_cls(data_width=self.bus.data_width, bursting=self.bus.bursting)
ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"), name=name) ram = ram_cls(size, bus=ram_bus, init=contents, read_only=("w" not in mode), name=name)
self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode)) self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
self.check_if_exists(name) self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format( self.logger.info("RAM {} {} {}.".format(
@ -902,7 +902,7 @@ class SoC(Module):
colorer(name), colorer(name),
colorer(f"0x{4*len(contents):x}"))) colorer(f"0x{4*len(contents):x}")))
getattr(self, name).mem.init = contents getattr(self, name).mem.init = contents
if auto_size and self.bus.regions[name].mode == "r": if auto_size and "w" not in self.bus.regions[name].mode:
self.logger.info("Auto-Resizing ROM {} from {} to {}.".format( self.logger.info("Auto-Resizing ROM {} from {} to {}.".format(
colorer(name), colorer(name),
colorer(f"0x{self.bus.regions[name].size:x}"), colorer(f"0x{self.bus.regions[name].size:x}"),