doc: common scheduling models
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Sebastien Bourdeauducq
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1972de0c59
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@ -8,6 +8,9 @@ Actors communicate by exchanging data units called tokens. A token contains arbi
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Actors
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******
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Actors and endpoints
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====================
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Actors in Migen are implemented in FHDL. This low-level approach maximizes the practical flexibility: for example, an actor can manipulate the bus signals to implement a DMA master in order to read data from system memory.
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Token exchange ports of actors are called endpoints. Endpoints are unidirectional and can be sources (which transmit tokens out of the actor) or sinks (which receive tokens into the actor).
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@ -40,14 +43,14 @@ Actors are derived from the the ``migen.flow.actor.Actor`` base class. The const
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An endpoint description is a triple consisting of:
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* The endpoint's name.
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* A reference to the ``migen.flow.actor.Sink`` or the ``migen.flow.actor.Source`` class, defining the token direction of the endpoint.
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* The layout of the data record that the endpoint is dealing with.
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* The endpoint's name.
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* A reference to the ``migen.flow.actor.Sink`` or the ``migen.flow.actor.Source`` class, defining the token direction of the endpoint.
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* The layout of the data record that the endpoint is dealing with.
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Record layouts are a list of fields. Each field is described by a pair consisting of:
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* The field's name.
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* Either a BV object (see :ref:`bv`) if the field is a bit vector, or another record layout if the field is a lower-level record.
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* The field's name.
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* Either a BV object (see :ref:`bv`) if the field is a bit vector, or another record layout if the field is a lower-level record.
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For example, this code: ::
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@ -57,40 +60,58 @@ For example, this code: ::
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creates an actor with:
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* One sink named ``operands`` accepting data structured as a 16-bit field ``a`` and a 16-bit field ``b``. Note that this is functionally different from having two endpoints ``a`` and ``b``, each accepting a single 16-bit field. With a single endpoint, the data is strobed when *both* ``a`` and ``b`` are valid, and ``a`` and ``b`` are *both* acknowledged *atomically*. With two endpoints, the actor has to deal with accepting ``a`` and ``b`` independently. Plumbing actors (see :ref:`plumbing`) and abstract networks (see :ref:`actornetworks`) provide a systematic way of converting between these two behaviours, so user actors should implement the behaviour that results in the simplest or highest performance design.
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* One source named ``result`` transmitting a single 17-bit field named ``r``.
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* One sink named ``operands`` accepting data structured as a 16-bit field ``a`` and a 16-bit field ``b``. Note that this is functionally different from having two endpoints ``a`` and ``b``, each accepting a single 16-bit field. With a single endpoint, the data is strobed when *both* ``a`` and ``b`` are valid, and ``a`` and ``b`` are *both* acknowledged *atomically*. With two endpoints, the actor has to deal with accepting ``a`` and ``b`` independently. Plumbing actors (see :ref:`plumbing`) and abstract networks (see :ref:`actornetworks`) provide a systematic way of converting between these two behaviours, so user actors should implement the behaviour that results in the simplest or highest performance design.
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* One source named ``result`` transmitting a single 17-bit field named ``r``.
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Implementing the functionality of the actor can be done in two ways:
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* Overloading the ``get_fragment`` method.
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* Overloading both the ``get_control_fragment`` and ``get_process_fragment`` methods. The ``get_control_fragment`` method should return a fragment that manipulates the control signals (strobes, acknowledgements and the actor's busy signal) while ``get_process_fragment`` should return a fragment that manipulates the token payload. Overloading ``get_control_fragment`` alone allows you to define abstract actor classes implementing a given scheduling model. Migen comes with a library of such abstract classes for the most common schedules (see :ref:`schedmod`).
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* Overloading the ``get_fragment`` method.
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* Overloading both the ``get_control_fragment`` and ``get_process_fragment`` methods. The ``get_control_fragment`` method should return a fragment that manipulates the control signals (strobes, acknowledgements and the actor's busy signal) while ``get_process_fragment`` should return a fragment that manipulates the token payload. Overloading ``get_control_fragment`` alone allows you to define abstract actor classes implementing a given scheduling model. Migen comes with a library of such abstract classes for the most common schedules (see :ref:`schedmod`).
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Accessing the endpoints is done via the ``endpoints`` dictionary, which is keyed by endpoint names and contains instances of the ``migen.flow.actor.Endpoint`` class. The latter holds:
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* A signal object ``stb``.
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* A signal object ``ack``.
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* The data payload ``token``. The individual fields are the items (in the Python sense) of this object.
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* A signal object ``stb``.
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* A signal object ``ack``.
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* The data payload ``token``. The individual fields are the items (in the Python sense) of this object.
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Busy signal
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===========
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The basic actor class creates a ``busy`` control signal that actor implementations should drive.
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This signal represents whether the actor's state holds information that will cause the completion of the transmission of output tokens. For example:
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* A "buffer" actor that simply registers and forwards incoming tokens should drive 1 on ``busy`` when its register contains valid data pending acknowledgement by the receiving actor, and 0 otherwise.
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* An actor sequenced by a finite state machine should drive ``busy`` to 1 whenever the state machine leaves its idle state.
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* An actor made of combinatorial logic is stateless and should tie ``busy`` to 0.
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.. _schedmod:
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Common scheduling models
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========================
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For the simplest and most common scheduling cases, Migen provides logic to generate the handshake signals and the busy signal. This is done through abstract actor classes that overload ``get_control_fragment`` only, and the user should overload ``get_process_fragment`` to implement the actor's payload.
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These classes are usable only when the actor has exactly one sink and one source (but those endpoints can contain an arbitrary data structure), and in the cases listed below.
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Combinatorial
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-------------
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The actor datapath is made entirely of combinatorial logic. The handshake signals pass through. A small integer adder would use this model.
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This model is implemented by the ``migen.flow.actor.CombinatorialActor`` class. There are no parameters or additional control signals.
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N-sequential
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------------
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The actor consumes one token at its input, and it produces one output token after N cycles. It cannot accept new input tokens until it has produced its output. A multicycle integer divider would use this model.
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This model is implemented by the ``migen.flow.actor.SequentialActor`` class. The constructor of this class takes as parameter the number of cycles N. The class provides an extra control signal ``trigger`` that pulses to 1 for one cycle when the actor should register the inputs and start its processing. The actor is then expected to provide an output after the N cycles and hold it constant until the next trigger pulse.
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N-pipelined
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-----------
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This is similar to the sequential model, but the actor can always accept new input tokens. It produces an output token N cycles of latency after accepting an input token. A pipelined multiplier would use this model.
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This model is implemented by the ``migen.flow.actor.PipelinedActor`` class. The constructor takes the number of pipeline stages N. There is an extra control signal ``pipe_ce`` that should enable or disable all synchronous statements in the datapath (i.e. it is the common clock enable signal for all the registers forming the pipeline stages).
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The Migen actor library
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***********************
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70
doc/fhdl.rst
70
doc/fhdl.rst
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@ -19,9 +19,9 @@ Bit vector (BV)
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===============
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The bit vector (BV) object defines if a constant or signal is signed or unsigned, and how many bits it has. This is useful e.g. to:
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* determine when to perform sign extension (FHDL uses the same rules as Verilog).
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* determine the size of registers.
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* determine how many bits should be used by each value in concatenations.
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* Determine when to perform sign extension (FHDL uses the same rules as Verilog).
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* Determine the size of registers.
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* Determine how many bits should be used by each value in concatenations.
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Constant
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========
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@ -38,10 +38,10 @@ The main point of the signal object is that it is identified by its Python ID (a
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The properties of a signal object are:
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* a bit vector description
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* a name, used as a hint for the V*HDL back-end name mangler.
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* a boolean "variable". If true, the signal will behave like a VHDL variable, or a Verilog reg that uses blocking assignment. This parameter only has an effect when the signal's value is modified in a synchronous statement.
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* the signal's reset value. It must be an integer, and defaults to 0. When the signal's value is modified with a synchronous statement, the reset value is the initialization value of the associated register. When the signal is assigned to in a conditional combinatorial statement (``If`` or ``Case``), the reset value is the value that the signal has when no condition that causes the signal to be driven is verified. This enforces the absence of latches in designs. If the signal is permanently driven using a combinatorial statement, the reset value has no effect.
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* A bit vector description
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* A name, used as a hint for the V*HDL back-end name mangler.
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* A boolean "variable". If true, the signal will behave like a VHDL variable, or a Verilog reg that uses blocking assignment. This parameter only has an effect when the signal's value is modified in a synchronous statement.
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* The signal's reset value. It must be an integer, and defaults to 0. When the signal's value is modified with a synchronous statement, the reset value is the initialization value of the associated register. When the signal is assigned to in a conditional combinatorial statement (``If`` or ``Case``), the reset value is the value that the signal has when no condition that causes the signal to be driven is verified. This enforces the absence of latches in designs. If the signal is permanently driven using a combinatorial statement, the reset value has no effect.
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The sole purpose of the name property is to make the generated V*HDL code easier to understand and debug. From a purely functional point of view, it is perfectly OK to have several signals with the same name property. The back-end will generate a unique name for each object. If no name property is specified, Migen will analyze the code that created the signal object, and try to extract the variable or member name from there. For example, the following statements will create one or several signals named "bar": ::
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@ -125,20 +125,20 @@ Instances
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=========
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Instance objects represent the parametrized instantiation of a V*HDL module, and the connection of its ports to FHDL signals. They are useful in a number of cases:
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* reusing legacy or third-party V*HDL code.
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* using special FPGA features (DCM, ICAP, ...).
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* implementing logic that cannot be expressed with FHDL (asynchronous circuits, ...).
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* breaking down a Migen system into multiple sub-systems, possibly using different clock domains.
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* Reusing legacy or third-party V*HDL code.
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* Using special FPGA features (DCM, ICAP, ...).
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* Implementing logic that cannot be expressed with FHDL (asynchronous circuits, ...).
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* Breaking down a Migen system into multiple sub-systems, possibly using different clock domains.
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The properties of the instance object are:
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* the type of the instance (i.e. name of the instantiated module).
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* a list of output ports of the instantiated module. Each element of the list is a pair containing a string, which is the name of the module's port, and either an existing signal (on which the port will be connected to) or a BV (which will cause the creation of a new signal).
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* a list of input ports (likewise).
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* a list of (name, value) pairs for the parameters ("generics" in VHDL) of the module.
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* the name of the clock port of the module (if any). If this is specified, the port will be connected to the system clock.
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* the name of the reset port of the module (likewise).
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* the name of the instance (can be mangled like signal names).
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* The type of the instance (i.e. name of the instantiated module).
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* A list of output ports of the instantiated module. Each element of the list is a pair containing a string, which is the name of the module's port, and either an existing signal (on which the port will be connected to) or a BV (which will cause the creation of a new signal).
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* A list of input ports (likewise).
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* A list of (name, value) pairs for the parameters ("generics" in VHDL) of the module.
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* The name of the clock port of the module (if any). If this is specified, the port will be connected to the system clock.
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* The name of the reset port of the module (likewise).
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* The name of the instance (can be mangled like signal names).
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Memories
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========
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@ -146,21 +146,21 @@ Memories (on-chip SRAM) are supported using a mechanism similar to instances.
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A memory object has the following parameters:
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* the width, which is the number of bits in each word.
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* the depth, which represents the number of words in the memory.
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* an optional list of integers used to initialize the memory.
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* a list of port descriptions.
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* The width, which is the number of bits in each word.
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* The depth, which represents the number of words in the memory.
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* An optional list of integers used to initialize the memory.
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* A list of port descriptions.
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Each port description contains:
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* the address signal (mandatory).
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* the data read signal (mandatory).
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* the write enable signal (optional). If the port is using masked writes, the width of the write enable signal should match the number of sub-words.
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* the data write signal (iff there is a write enable signal).
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* whether reads are synchronous (default) or asynchronous.
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* the read enable port (optional, ignored for asynchronous ports).
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* the write granularity (default 0), which defines the number of bits in each sub-word. If it is set to 0, the port is using whole-word writes only and the width of the write enable signal must be 1. This parameter is ignored if there is no write enable signal.
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* the mode of the port (default ``WRITE_FIRST``, ignored for asynchronous ports). It can be:
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* The address signal (mandatory).
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* The data read signal (mandatory).
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* The write enable signal (optional). If the port is using masked writes, the width of the write enable signal should match the number of sub-words.
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* The data write signal (iff there is a write enable signal).
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* Whether reads are synchronous (default) or asynchronous.
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* The read enable port (optional, ignored for asynchronous ports).
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* The write granularity (default 0), which defines the number of bits in each sub-word. If it is set to 0, the port is using whole-word writes only and the width of the write enable signal must be 1. This parameter is ignored if there is no write enable signal.
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* The mode of the port (default ``WRITE_FIRST``, ignored for asynchronous ports). It can be:
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* ``READ_FIRST``: during a write, the previous value is read.
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* ``WRITE_FIRST``: the written value is returned.
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@ -172,11 +172,11 @@ Fragments
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*********
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A "fragment" is a unit of logic, which is composed of:
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* a list of combinatorial statements.
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* a list of synchronous statements.
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* a list of instances.
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* a list of memories.
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* a list of simulation functions (see :ref:`simulating`).
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* A list of combinatorial statements.
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* A list of synchronous statements.
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* A list of instances.
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* A list of memories.
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* A list of simulation functions (see :ref:`simulating`).
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Fragments can reference arbitrary signals, including signals that are referenced in other fragments. Fragments can be combined using the "+" operator, which returns a new fragment containing the concatenation of each pair of lists.
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@ -52,3 +52,7 @@ Installing Migen
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Either run the ``setup.py`` installation script or simply set ``PYTHONPATH`` to the root of the source directory.
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For simulation support, an extra step is needed. See :ref:`vpisetup`.
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Feedback
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********
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Feedback concerning Migen or this manual should be sent to the Milkymist developers' mailing list at devel@lists.milkymist.org.
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