targets/kc705: use PLL for clocking

This commit is contained in:
Sebastien Bourdeauducq 2014-08-03 21:42:39 +08:00
parent 1a09eb7a19
commit 37968e649b
1 changed files with 36 additions and 12 deletions

View File

@ -3,26 +3,50 @@ from migen.bus import wishbone
from misoclib.gensoc import GenSoC, IntegratedBIOS
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
clk200 = platform.request("clk200")
clk200_se = Signal()
self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
pll_locked = Signal()
pll_fb = Signal()
pll_clk1x = Signal()
self.specials += Instance("PLLE2_BASE",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
# VCO @ 1GHz
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 125MHz
p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_clk1x,
p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=270.0, #o_CLKOUT1=,
p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
)
self.specials += Instance("BUFG", i_I=pll_clk1x, o_O=self.cd_sys.clk)
self.specials += Instance("FD", p_INIT=1, i_D=~pll_locked,
i_C=self.cd_sys.clk, o_Q=self.cd_sys.rst)
class BaseSoC(GenSoC, IntegratedBIOS):
default_platform = "kc705"
def __init__(self, platform, **kwargs):
GenSoC.__init__(self, platform,
clk_freq=156*1000000, cpu_reset_address=0,
clk_freq=125*1000000, cpu_reset_address=0,
**kwargs)
IntegratedBIOS.__init__(self)
clk200 = platform.request("clk156")
self.specials += Instance("IBUFGDS",
i_I=clk200.p,
i_IB=clk200.n,
o_O=ClockSignal()
)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_pwr_on = ClockDomain(reset_less=True)
self.comb += self.cd_pwr_on.clk.eq(self.cd_sys.clk)
self.cd_sys.rst.reset = 1
self.sync.pwr_on += self.cd_sys.rst.eq(0)
self.submodules.crg = _CRG(platform)
self.submodules.usermem = wishbone.SRAM(64*1024)
self.add_wb_slave(lambda a: a[27:29] == 2, self.usermem.bus)