global: pep8 (E231)
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@ -50,10 +50,10 @@ def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
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# Enforce use of SystemVerilog (Quartus does not support global parameters in Verilog)
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if language == "verilog":
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language = "systemverilog"
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qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n"
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qsf_contents += "set_global_assignment -name "+ language.upper() + "_FILE " + filename.replace("\\", "/") + "\n"
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for path in vincpaths:
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qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\","/") + "\n"
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qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\", "/") + "\n"
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qsf_contents += _build_qsf(named_sc, named_pc)
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qsf_contents += "set_global_assignment -name DEVICE " + device
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@ -40,7 +40,7 @@ _io = [
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Subsignal("cas_n", Pins("L1")),
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Subsignal("we_n", Pins("C2")),
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Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")),
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Subsignal("dm", Pins("R6","T5")),
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Subsignal("dm", Pins("R6 T5")),
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IOStandard("3.3-V LVTTL")
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),
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@ -100,7 +100,7 @@ make -j -C obj_dir/ -f Vdut.mk Vdut
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build_script_file = "build_" + build_name + ".sh"
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tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
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_build_tb(platform, vns, serial, os.path.join("..", sim_path,"dut_tb.cpp"))
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_build_tb(platform, vns, serial, os.path.join("..", sim_path, "dut_tb.cpp"))
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if verbose:
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r = subprocess.call(["bash", build_script_file])
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else:
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@ -137,7 +137,7 @@ def _generate_cells(f):
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return [_Cell(k, v) for k, v in cell_dict.items()]
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def _generate_instances(f,ns):
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def _generate_instances(f, ns):
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instances = []
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for special in f.specials:
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if isinstance(special, Instance):
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@ -17,7 +17,7 @@ class RoundRobin(Module):
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cases = {}
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for i in range(n):
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switch = []
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for j in reversed(range(i+1,i+n)):
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for j in reversed(range(i+1, i+n)):
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t = j % n
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switch = [
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If(self.request[t],
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