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Merge pull request #240 from danielkucera/patch-1

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more understandable error when missing a memory
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enjoy-digital 2019-08-13 10:34:50 +02:00 committed by GitHub
commit 383c05e239
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litex/soc/integration/soc_core.py
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@ -501,7 +501,7 @@ class SoCCore(Module):
if self.cpu_type is not None:
for mem in "rom", "sram":
if mem not in registered_mems:
raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem))
raise FinalizeError("CPU needs \"{}\" to be registered with SoC.register_mem()".format(mem))
# Add the Wishbone Masters/Slaves interconnect
if len(self._wb_masters):