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soc/cores/clock: add CycloneVPLL.

This commit is contained in:
Florent Kermarrec 2020-04-07 17:24:12 +02:00
parent ab4906ea3b
commit 383fcd36d6
2 changed files with 48 additions and 5 deletions
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45
litex/soc/cores/clock.py
View File

@ -815,9 +815,44 @@ class CycloneIVPLL(AlteraClocking):
"-9L": (5e6, 256e6),
}[speedgrade]
self.clko_freq_range = {
"-6" : (0, 472.5e6),
"-7" : (0, 450e6),
"-8" : (0, 402.5e6),
"-8L": (0, 362e6),
"-9L": (0, 265e6),
"-6" : (0e6, 472.5e6),
"-7" : (0e6, 450e6),
"-8" : (0e6, 402.5e6),
"-8L": (0e6, 362e6),
"-9L": (0e6, 265e6),
}[speedgrade]
# Altera / CycloneV --------------------------------------------------------------------------------
class CycloneVPLL(AlteraClocking):
nclkouts_max = 5
n_div_range = (1, 512+1)
m_div_range = (1, 512+1)
c_div_range = (1, 512+1)
clkin_pfd_freq_range = (5e6, 325e6) # FIXME: use
clkfin_pfd_freq_range = (50e6, 160e6) # FIXME: use
def __init__(self, speedgrade="-C6"):
self.logger = logging.getLogger("CycloneIVPLL")
self.logger.info("Creating CycloneIVPLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
AlteraClocking.__init__(self)
self.clkin_freq_range = {
"-C6" : (5e6, 670e6),
"-C7" : (5e6, 622e6),
"-I7" : (5e6, 622e6),
"-C8" : (5e6, 622e6),
"-A7" : (5e6, 500e6),
}[speedgrade]
self.vco_freq_range = {
"-C6" : (5e6, 1600e6),
"-C7" : (5e6, 1600e6),
"-I7" : (5e6, 1600e6),
"-C8" : (5e6, 1300e6),
"-A7" : (5e6, 1300e6),
}[speedgrade]
self.clko_freq_range = {
"-C6" : (0e6, 550e6),
"-C7" : (0e6, 550e6),
"-I7" : (0e6, 550e6),
"-C8" : (0e6, 460e6),
"-A7" : (0e6, 460e6),
}[speedgrade]

8
test/test_clock.py
View File

@ -75,3 +75,11 @@ class TestClock(unittest.TestCase):
for i in range(pll.nclkouts_max):
pll.create_clkout(ClockDomain("clkout{}".format(i)), 100e6)
pll.compute_config()
# Altera / CycloneV
def test_cyclonevpll(self):
pll = CycloneVPLL()
pll.register_clkin(Signal(), 50e6)
for i in range(pll.nclkouts_max):
pll.create_clkout(ClockDomain("clkout{}".format(i)), 100e6)
pll.compute_config()