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etherbone: record wip
This commit is contained in:
Florent Kermarrec
parent
abe6d87438
commit
384fc3c868
2 changed files with 136 additions and 56 deletions
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@ -274,6 +274,17 @@ def eth_etherbone_record_description(dw):
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param_layout = _layout_from_header(etherbone_record_header)
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return EndpointDescription(payload_layout, param_layout, packetized=True)
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def eth_etherbone_mmap_description(dw):
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payload_layout = [
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("data_addr", max(32, dw)),
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]
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param_layout = [
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("count", 8),
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("base_addr", 32),
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("be", dw//8)
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]
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return EndpointDescription(payload_layout, param_layout, packetized=True)
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# Generic classes
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class Port:
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def connect(self, port):
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@ -377,10 +388,9 @@ class PacketBuffer(Module):
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return EndpointDescription(layout)
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cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
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self.submodules += cmd_fifo
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self.comb += [
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cmd_fifo.sink.stb.eq(sink_status.done),
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cmd_fifo.sink.error.eq(sink.error)
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]
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self.comb += cmd_fifo.sink.stb.eq(sink_status.done)
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if hasattr(sink, "error"):
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self.comb += cmd_fifo.sink.error.eq(sink.error)
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# data
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data_fifo = SyncFIFO(description, data_depth, buffered=True)
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@ -406,9 +416,14 @@ class PacketBuffer(Module):
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NextState("OUTPUT")
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)
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)
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if hasattr(source, "error"):
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source_error = self.source.error
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else:
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source_error = Signal()
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fsm.act("OUTPUT",
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Record.connect(data_fifo.source, self.source),
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self.source.error.eq(cmd_fifo.source.error),
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source_error.eq(cmd_fifo.source.error),
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If(source_status.done,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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@ -6,83 +6,148 @@ class LiteEthEtherboneRecordPacketizer(LiteEthPacketizer):
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def __init__(self):
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LiteEthPacketizer.__init__(self,
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eth_etherbone_record_description(32),
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eth_raw_description(32),
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eth_etherbone_packet_user_description(32),
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etherbone_record_header,
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etherbone_record_header_len)
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class LiteEthEtherboneRecordTX(Module):
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def __init__(self):
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self.sink = sink = Sink(eth_etherbone_record_description(32))
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self.source = source = Source(eth_raw_description(32))
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###
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self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
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self.comb += Record.connect(sink, packetizer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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packetizer.source.ack.eq(1),
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If(packetizer.source.stb & packetizer.source.sop,
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packetizer.source.ack.eq(0),
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NextState("SEND")
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)
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)
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fsm.act("SEND",
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Record.connect(packetizer.source, source),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthEtherboneRecordDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_raw_description(32),
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eth_etherbone_packet_user_description(32),
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eth_etherbone_record_description(32),
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etherbone_record_header,
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etherbone_record_header_len)
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class LiteEthEtherboneRecordRX(Module):
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class LiteEthEtherboneRecordReceiver(Module):
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def __init__(self):
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self.sink = sink = Sink(eth_raw_description(32))
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self.source = source = Source(eth_etherbone_record_description(32))
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self.sink = sink = Sink(eth_etherbone_record_description(32))
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self.write_source = write_source = Source(eth_etherbone_mmap_description(32))
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self.read_source = read_source = Source(eth_etherbone_mmap_description(32))
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###
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self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
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self.comb += Record.connect(sink, depacketizer.sink)
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self.submodules.base_addr = base_addr = FlipFlop(32)
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self.comb += base_addr.d.eq(sink.data)
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self.submodules.counter = counter = Counter(max=512)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.sop,
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depacketizer.source.ack.eq(0),
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NextState("CHECK")
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sink.ack.eq(1),
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counter.reset.eq(1),
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If(sink.stb & sink.sop,
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base_addr.ce.eq(1),
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If(sink.wcount,
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NextState("RECEIVE_READS")
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).Elif(sink.rcount,
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NextState("RECEIVE_READS")
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)
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)
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)
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valid = Signal()
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self.sync += valid.eq(1) # XXX
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fsm.act("CHECK",
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If(valid,
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NextState("PRESENT")
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).Else(
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NextState("DROP")
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fsm.act("RECEIVE_WRITES",
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write_source.stb.eq(sink.stb),
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write_source.sop.eq(counter.value == 0),
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write_source.eop.eq(counter.value == sink.wcount-1),
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write_source.count.eq(sink.wcount),
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write_source.base_addr.eq(base_addr.q),
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write_source.data_addr.eq(sink.data),
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sink.ack.eq(write_source.ack),
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If(write_source.stb & write_source.ack,
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counter.ce.eq(1),
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If(write_source.eop,
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If(sink.rcount,
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NextState("RECEIVE_BASE_RET_ADDR")
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).Else(
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NextState("IDLE")
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)
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)
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)
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)
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fsm.act("PRESENT",
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Record.connect(depacketizer.source, source),
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fsm.act("RECEIVE_BASE_RET_ADDR",
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counter.reset.eq(1),
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If(sink.stb & sink.sop,
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base_addr.ce.eq(1),
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NextState("RECEIVE_READS")
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)
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)
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fsm.act("RECEIVE_READS",
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read_source.stb.eq(sink.stb),
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read_source.sop.eq(counter.value == 0),
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read_source.eop.eq(counter.value == sink.rcount-1),
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read_source.count.eq(sink.rcount),
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read_source.base_addr.eq(base_addr.q),
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read_source.data_addr.eq(sink.data),
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sink.ack.eq(read_source.ack),
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If(read_source.stb & read_source.ack,
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counter.ce.eq(1),
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If(read_source.eop,
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NextState("IDLE")
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)
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)
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)
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# Note: for now only support writes from the FPGA
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class LiteEthEtherboneRecordSender(Module):
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def __init__(self):
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self.wr_sink = wr_sink = Sink(eth_etherbone_mmap_description(32))
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self.rd_sink = rd_sink = Sink(eth_etherbone_mmap_description(32))
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self.source = source = Source(eth_etherbone_record_description(32))
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###
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self.submodules.wr_buffer = wr_buffer = PacketBuffer(eth_etherbone_mmap_description(32), 512)
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self.comb += Record.connect(wr_sink, wr_buffer.sink)
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self.submodules.base_addr = base_addr = FlipFlop(32)
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self.comb += base_addr.d.eq(wr_buffer.source.data_addr)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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wr_buffer.source.ack.eq(1),
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If(wr_buffer.source.stb & wr_buffer.source.sop,
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wr_buffer.source.ack.eq(0),
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base_addr.ce.eq(1),
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NextState("SEND_BASE_ADDRESS")
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)
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)
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self.comb += [
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source.byte_enable.eq(wr_buffer.source.be),
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source.wcount.eq(wr_buffer.source.count),
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source.rcount.eq(0)
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]
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fsm.act("SEND_BASE_ADDRESS",
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source.stb.eq(wr_buffer.source.stb),
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source.sop.eq(1),
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source.eop.eq(0),
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source.data.eq(base_addr.q),
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If(source.ack,
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NextState("SEND_DATA")
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)
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)
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fsm.act("SEND_DATA",
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source.stb.eq(wr_buffer.source.stb),
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source.sop.eq(0),
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source.eop.eq(wr_buffer.source.eop),
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source.data.eq(wr_buffer.source.data_addr),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("DROP",
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
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NextState("IDLE")
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)
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)
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# Note: for now only support 1 record per packet
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class LiteEthEtherboneRecord(Module):
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def __init__(self):
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self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
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self.source = source = Sink(eth_etherbone_packet_user_description(32))
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###
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self.submodules.record_tx = record_tx = LiteEthEtherboneRecordTX()
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self.submodules.record_rx = record_rx = LiteEthEtherboneRecordRX()
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self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
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self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver()
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self.comb += [
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Record.connect(sink, depacketizer.sink),
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Record.connect(depacketizer.source, receiver.sink)
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]
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self.submodules.sender = sender = LiteEthEtherboneRecordSender()
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self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
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self.comb += [
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Record.connect(sender.source, packetizer.sink),
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Record.connect(packetizer.source, source)
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]
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