software/libbase/isr.c: Cleanup code a bit.
This commit is contained in:
Florent Kermarrec
parent
6164a55c6b
commit
38e060c354
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@ -3,7 +3,6 @@
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// This file is Copyright (c) 2020 Raptor Engineering, LLC <sales@raptorengineering.com>
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// License: BSD
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#include <generated/csr.h>
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#include <generated/soc.h>
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#include <irq.h>
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@ -19,64 +18,73 @@ void isr(void);
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#ifdef CONFIG_CPU_HAS_INTERRUPT
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#if defined(__blackparrot__) /*TODO: Update this function for BP*/ //
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/*************************************/
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/* ISR Handling for BlackParrot CPU. */
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/*************************************/
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#if defined(__blackparrot__) /*TODO: Update this function for BP.*/
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void isr(void)
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{
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static int onetime = 0;
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if ( onetime == 0){
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printf("ISR blackparrot\n");
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printf("TRAP!!\n");
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onetime++;
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}
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static int onetime = 0;
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if (onetime == 0) {
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printf("ISR blackparrot\n");
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printf("TRAP!!\n");
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onetime++;
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}
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}
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/***********************************************************/
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/* ISR and PLIC Initialization for RISC-V PLIC-based CPUs. */
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/***********************************************************/
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#elif defined(__riscv_plic__)
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// PLIC initialization.
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void plic_init(void);
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/* PLIC initialization. */
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void plic_init(void)
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{
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int i;
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int i;
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/* Set priorities for the first 8 external interrupts to 1. */
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for (i = 0; i < 8; i++)
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*((unsigned int *)(PLIC_BASE + PLIC_EXT_IRQ_BASE + i)) = 1;
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// Set priorities for the first 8 external interrupts to 1.
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for (i = 0; i < 8; i++)
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*((unsigned int *)PLIC_BASE + PLIC_EXT_IRQ_BASE + i) = 1;
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/* Enable the first 8 external interrupts. */
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*((unsigned int *)PLIC_ENABLED) = 0xff << PLIC_EXT_IRQ_BASE;
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// Enable the first 8 external interrupts
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*((unsigned int *)PLIC_ENABLED) = 0xff << PLIC_EXT_IRQ_BASE;
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// Set priority threshold to 0 (any priority > 0 triggers an interrupt).
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*((unsigned int *)PLIC_THRSHLD) = 0;
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/* Set priority threshold to 0 (any priority > 0 triggers an interrupt). */
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*((unsigned int *)PLIC_THRSHLD) = 0;
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}
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// Interrupt Service Routine.
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/* Interrupt Service Routine. */
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void isr(void)
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{
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unsigned int claim;
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unsigned int claim;
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// Claim and handle pending interrupts.
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while ((claim = *((unsigned int *)PLIC_CLAIM))) {
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switch (claim - PLIC_EXT_IRQ_BASE) {
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case UART_INTERRUPT:
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uart_isr(); // Handle UART interrupt.
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break;
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default:
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// Unhandled interrupt source, print diagnostic information.
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printf("## PLIC: Unhandled claim: %d\n", claim);
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printf("# plic_enabled: %08x\n", irq_getmask());
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printf("# plic_pending: %08x\n", irq_pending());
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printf("# mepc: %016lx\n", csrr(mepc));
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printf("# mcause: %016lx\n", csrr(mcause));
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printf("# mtval: %016lx\n", csrr(mtval));
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printf("# mie: %016lx\n", csrr(mie));
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printf("# mip: %016lx\n", csrr(mip));
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printf("###########################\n\n");
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break;
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}
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// Acknowledge the interrupt.
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*((unsigned int *)PLIC_CLAIM) = claim;
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}
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/* Claim and handle pending interrupts. */
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while ((claim = *((unsigned int *)PLIC_CLAIM))) {
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switch (claim - PLIC_EXT_IRQ_BASE) {
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case UART_INTERRUPT:
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uart_isr(); /* Handle UART interrupt. */
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break;
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default:
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/* Unhandled interrupt source, print diagnostic information. */
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printf("## PLIC: Unhandled claim: %d\n", claim);
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printf("# plic_enabled: %08x\n", irq_getmask());
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printf("# plic_pending: %08x\n", irq_pending());
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printf("# mepc: %016lx\n", csrr(mepc));
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printf("# mcause: %016lx\n", csrr(mcause));
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printf("# mtval: %016lx\n", csrr(mtval));
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printf("# mie: %016lx\n", csrr(mie));
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printf("# mip: %016lx\n", csrr(mip));
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printf("###########################\n\n");
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break;
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}
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/* Acknowledge the interrupt. */
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*((unsigned int *)PLIC_CLAIM) = claim;
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}
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}
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#elif defined(__cv32e40p__) || defined(__cv32e41p__)
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/************************************************/
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/* ISR Handling for CV32E40P and CV32E41P CPUs. */
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/************************************************/
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#elif defined(__cv32e40p__) || defined(__cv32e41p__)
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#define FIRQ_OFFSET 16
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#define IRQ_MASK 0x7FFFFFFF
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@ -90,119 +98,124 @@ void isr(void)
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if (csrr(mcause) & 0x80000000) {
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#ifndef UART_POLLING
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if (cause == (UART_INTERRUPT+FIRQ_OFFSET)){
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if (cause == (UART_INTERRUPT + FIRQ_OFFSET)) {
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uart_isr();
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}
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#endif
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} else {
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#ifdef RISCV_TEST
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int gp;
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asm volatile ("mv %0, gp" : "=r"(gp));
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asm volatile("mv %0, gp" : "=r"(gp));
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printf("E %d\n", cause);
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if (cause == INVINST) {
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printf("Inv Instr\n");
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for(;;);
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for (;;);
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}
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if (cause == ECALL) {
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printf("Ecall (gp: %d)\n", gp);
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csrw(mepc, csrr(mepc)+4);
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csrw(mepc, csrr(mepc) + 4);
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}
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#endif
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}
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}
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/***********************************/
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/* ISR Handling for Microwatt CPU. */
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/***********************************/
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#elif defined(__microwatt__)
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void isr(uint64_t vec)
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{
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if (vec == 0x900)
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return isr_dec();
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if (vec == 0x900)
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return isr_dec();
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if (vec == 0x500) {
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// Read interrupt source
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uint32_t xirr = xics_icp_readw(PPC_XICS_XIRR);
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uint32_t irq_source = xirr & 0x00ffffff;
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if (vec == 0x500) {
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/* Read interrupt source. */
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uint32_t xirr = xics_icp_readw(PPC_XICS_XIRR);
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uint32_t irq_source = xirr & 0x00ffffff;
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__attribute__((unused)) unsigned int irqs;
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__attribute__((unused)) unsigned int irqs;
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// Handle IPI interrupts separately
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if (irq_source == 2) {
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// IPI interrupt
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xics_icp_writeb(PPC_XICS_MFRR, 0xff);
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}
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else {
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// External interrupt
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irqs = irq_pending() & irq_getmask();
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/* Handle IPI interrupts separately. */
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if (irq_source == 2) {
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/* IPI interrupt. */
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xics_icp_writeb(PPC_XICS_MFRR, 0xff);
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} else {
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/* External interrupt. */
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irqs = irq_pending() & irq_getmask();
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#ifndef UART_POLLING
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if(irqs & (1 << UART_INTERRUPT))
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uart_isr();
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if (irqs & (1 << UART_INTERRUPT))
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uart_isr();
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#endif
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}
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}
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// Clear interrupt
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xics_icp_writew(PPC_XICS_XIRR, xirr);
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/* Clear interrupt. */
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xics_icp_writew(PPC_XICS_XIRR, xirr);
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return;
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}
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return;
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}
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}
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void isr_dec(void)
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{
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// For now, just set DEC back to a large enough value to slow the flood of DEC-initiated timer interrupts
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mtdec(0x000000000ffffff);
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/* Set DEC back to a large enough value to slow the flood of DEC-initiated timer interrupts. */
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mtdec(0x000000000ffffff);
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}
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/*******************************************************/
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/* Generic ISR Handling for CPUs with Interrupt Table. */
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/*******************************************************/
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#else
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struct irq_table
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{
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isr_t isr;
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isr_t isr;
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} irq_table[CONFIG_CPU_INTERRUPTS];
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int irq_attach(unsigned int irq, isr_t isr)
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{
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if (irq >= CONFIG_CPU_INTERRUPTS) {
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printf("Inv irq %d\n", irq);
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return -1;
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}
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if (irq >= CONFIG_CPU_INTERRUPTS) {
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printf("Inv irq %d\n", irq);
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return -1;
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}
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unsigned int ie = irq_getie();
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irq_setie(0);
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irq_table[irq].isr = isr;
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irq_setie(ie);
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return irq;
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unsigned int ie = irq_getie();
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irq_setie(0);
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irq_table[irq].isr = isr;
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irq_setie(ie);
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return irq;
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}
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int irq_detach(unsigned int irq)
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{
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return irq_attach(irq, NULL);
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return irq_attach(irq, NULL);
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}
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/* Interrupt Service Routine. */
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void isr(void)
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{
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unsigned int irqs = irq_pending() & irq_getmask();
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unsigned int irqs = irq_pending() & irq_getmask();
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while (irqs)
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{
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const unsigned int irq = __builtin_ctz(irqs);
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if ((irq < CONFIG_CPU_INTERRUPTS) && irq_table[irq].isr)
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irq_table[irq].isr();
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else {
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irq_setmask(irq_getmask() & ~(1<<irq));
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printf("\n*** disabled spurious irq %d ***\n", irq);
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}
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irqs &= irqs - 1; // clear this irq (the first bit set)
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}
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while (irqs) {
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const unsigned int irq = __builtin_ctz(irqs);
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if ((irq < CONFIG_CPU_INTERRUPTS) && irq_table[irq].isr)
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irq_table[irq].isr();
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else {
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irq_setmask(irq_getmask() & ~(1 << irq));
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printf("\n*** disabled spurious irq %d ***\n", irq);
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}
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irqs &= irqs - 1; /* Clear this IRQ (the first bit set). */
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}
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}
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#endif
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#else
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#if defined(__microwatt__)
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void isr(uint64_t vec){};
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void isr(uint64_t vec) {};
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#else
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void isr(void){};
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void isr(void) {};
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#endif
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#endif
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