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software/libbase/isr.c: Cleanup code a bit.

This commit is contained in:
Florent Kermarrec 2024-06-14 11:47:02 +02:00
parent 6164a55c6b
commit 38e060c354
1 changed files with 110 additions and 97 deletions
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207
litex/soc/software/libbase/isr.c
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@ -3,7 +3,6 @@
// This file is Copyright (c) 2020 Raptor Engineering, LLC <sales@raptorengineering.com> // This file is Copyright (c) 2020 Raptor Engineering, LLC <sales@raptorengineering.com>
// License: BSD // License: BSD
#include <generated/csr.h> #include <generated/csr.h>
#include <generated/soc.h> #include <generated/soc.h>
#include <irq.h> #include <irq.h>
@ -19,64 +18,73 @@ void isr(void);
#ifdef CONFIG_CPU_HAS_INTERRUPT #ifdef CONFIG_CPU_HAS_INTERRUPT
#if defined(__blackparrot__) /*TODO: Update this function for BP*/ // /*************************************/
/* ISR Handling for BlackParrot CPU. */
/*************************************/
#if defined(__blackparrot__) /*TODO: Update this function for BP.*/
void isr(void) void isr(void)
{ {
static int onetime = 0; static int onetime = 0;
if ( onetime == 0){ if (onetime == 0) {
printf("ISR blackparrot\n"); printf("ISR blackparrot\n");
printf("TRAP!!\n"); printf("TRAP!!\n");
onetime++; onetime++;
} }
} }
/***********************************************************/
/* ISR and PLIC Initialization for RISC-V PLIC-based CPUs. */
/***********************************************************/
#elif defined(__riscv_plic__) #elif defined(__riscv_plic__)
// PLIC initialization. /* PLIC initialization. */
void plic_init(void);
void plic_init(void) void plic_init(void)
{ {
int i; int i;
/* Set priorities for the first 8 external interrupts to 1. */
for (i = 0; i < 8; i++)
*((unsigned int *)(PLIC_BASE + PLIC_EXT_IRQ_BASE + i)) = 1;
// Set priorities for the first 8 external interrupts to 1. /* Enable the first 8 external interrupts. */
for (i = 0; i < 8; i++) *((unsigned int *)PLIC_ENABLED) = 0xff << PLIC_EXT_IRQ_BASE;
*((unsigned int *)PLIC_BASE + PLIC_EXT_IRQ_BASE + i) = 1;
// Enable the first 8 external interrupts /* Set priority threshold to 0 (any priority > 0 triggers an interrupt). */
*((unsigned int *)PLIC_ENABLED) = 0xff << PLIC_EXT_IRQ_BASE; *((unsigned int *)PLIC_THRSHLD) = 0;
// Set priority threshold to 0 (any priority > 0 triggers an interrupt).
*((unsigned int *)PLIC_THRSHLD) = 0;
} }
// Interrupt Service Routine. /* Interrupt Service Routine. */
void isr(void) void isr(void)
{ {
unsigned int claim; unsigned int claim;
// Claim and handle pending interrupts. /* Claim and handle pending interrupts. */
while ((claim = *((unsigned int *)PLIC_CLAIM))) { while ((claim = *((unsigned int *)PLIC_CLAIM))) {
switch (claim - PLIC_EXT_IRQ_BASE) { switch (claim - PLIC_EXT_IRQ_BASE) {
case UART_INTERRUPT: case UART_INTERRUPT:
uart_isr(); // Handle UART interrupt. uart_isr(); /* Handle UART interrupt. */
break; break;
default: default:
// Unhandled interrupt source, print diagnostic information. /* Unhandled interrupt source, print diagnostic information. */
printf("## PLIC: Unhandled claim: %d\n", claim); printf("## PLIC: Unhandled claim: %d\n", claim);
printf("# plic_enabled: %08x\n", irq_getmask()); printf("# plic_enabled: %08x\n", irq_getmask());
printf("# plic_pending: %08x\n", irq_pending()); printf("# plic_pending: %08x\n", irq_pending());
printf("# mepc: %016lx\n", csrr(mepc)); printf("# mepc: %016lx\n", csrr(mepc));
printf("# mcause: %016lx\n", csrr(mcause)); printf("# mcause: %016lx\n", csrr(mcause));
printf("# mtval: %016lx\n", csrr(mtval)); printf("# mtval: %016lx\n", csrr(mtval));
printf("# mie: %016lx\n", csrr(mie)); printf("# mie: %016lx\n", csrr(mie));
printf("# mip: %016lx\n", csrr(mip)); printf("# mip: %016lx\n", csrr(mip));
printf("###########################\n\n"); printf("###########################\n\n");
break; break;
} }
// Acknowledge the interrupt. /* Acknowledge the interrupt. */
*((unsigned int *)PLIC_CLAIM) = claim; *((unsigned int *)PLIC_CLAIM) = claim;
} }
} }
#elif defined(__cv32e40p__) || defined(__cv32e41p__)
/************************************************/
/* ISR Handling for CV32E40P and CV32E41P CPUs. */
/************************************************/
#elif defined(__cv32e40p__) || defined(__cv32e41p__)
#define FIRQ_OFFSET 16 #define FIRQ_OFFSET 16
#define IRQ_MASK 0x7FFFFFFF #define IRQ_MASK 0x7FFFFFFF
@ -90,119 +98,124 @@ void isr(void)
if (csrr(mcause) & 0x80000000) { if (csrr(mcause) & 0x80000000) {
#ifndef UART_POLLING #ifndef UART_POLLING
if (cause == (UART_INTERRUPT+FIRQ_OFFSET)){ if (cause == (UART_INTERRUPT + FIRQ_OFFSET)) {
uart_isr(); uart_isr();
} }
#endif #endif
} else { } else {
#ifdef RISCV_TEST #ifdef RISCV_TEST
int gp; int gp;
asm volatile ("mv %0, gp" : "=r"(gp)); asm volatile("mv %0, gp" : "=r"(gp));
printf("E %d\n", cause); printf("E %d\n", cause);
if (cause == INVINST) { if (cause == INVINST) {
printf("Inv Instr\n"); printf("Inv Instr\n");
for(;;); for (;;);
} }
if (cause == ECALL) { if (cause == ECALL) {
printf("Ecall (gp: %d)\n", gp); printf("Ecall (gp: %d)\n", gp);
csrw(mepc, csrr(mepc)+4); csrw(mepc, csrr(mepc) + 4);
} }
#endif #endif
} }
} }
/***********************************/
/* ISR Handling for Microwatt CPU. */
/***********************************/
#elif defined(__microwatt__) #elif defined(__microwatt__)
void isr(uint64_t vec) void isr(uint64_t vec)
{ {
if (vec == 0x900) if (vec == 0x900)
return isr_dec(); return isr_dec();
if (vec == 0x500) { if (vec == 0x500) {
// Read interrupt source /* Read interrupt source. */
uint32_t xirr = xics_icp_readw(PPC_XICS_XIRR); uint32_t xirr = xics_icp_readw(PPC_XICS_XIRR);
uint32_t irq_source = xirr & 0x00ffffff; uint32_t irq_source = xirr & 0x00ffffff;
__attribute__((unused)) unsigned int irqs; __attribute__((unused)) unsigned int irqs;
// Handle IPI interrupts separately /* Handle IPI interrupts separately. */
if (irq_source == 2) { if (irq_source == 2) {
// IPI interrupt /* IPI interrupt. */
xics_icp_writeb(PPC_XICS_MFRR, 0xff); xics_icp_writeb(PPC_XICS_MFRR, 0xff);
} } else {
else { /* External interrupt. */
// External interrupt irqs = irq_pending() & irq_getmask();
irqs = irq_pending() & irq_getmask();
#ifndef UART_POLLING #ifndef UART_POLLING
if(irqs & (1 << UART_INTERRUPT)) if (irqs & (1 << UART_INTERRUPT))
uart_isr(); uart_isr();
#endif #endif
} }
// Clear interrupt /* Clear interrupt. */
xics_icp_writew(PPC_XICS_XIRR, xirr); xics_icp_writew(PPC_XICS_XIRR, xirr);
return; return;
} }
} }
void isr_dec(void) void isr_dec(void)
{ {
// For now, just set DEC back to a large enough value to slow the flood of DEC-initiated timer interrupts /* Set DEC back to a large enough value to slow the flood of DEC-initiated timer interrupts. */
mtdec(0x000000000ffffff); mtdec(0x000000000ffffff);
} }
/*******************************************************/
/* Generic ISR Handling for CPUs with Interrupt Table. */
/*******************************************************/
#else #else
struct irq_table struct irq_table
{ {
isr_t isr; isr_t isr;
} irq_table[CONFIG_CPU_INTERRUPTS]; } irq_table[CONFIG_CPU_INTERRUPTS];
int irq_attach(unsigned int irq, isr_t isr) int irq_attach(unsigned int irq, isr_t isr)
{ {
if (irq >= CONFIG_CPU_INTERRUPTS) { if (irq >= CONFIG_CPU_INTERRUPTS) {
printf("Inv irq %d\n", irq); printf("Inv irq %d\n", irq);
return -1; return -1;
} }
unsigned int ie = irq_getie(); unsigned int ie = irq_getie();
irq_setie(0); irq_setie(0);
irq_table[irq].isr = isr; irq_table[irq].isr = isr;
irq_setie(ie); irq_setie(ie);
return irq; return irq;
} }
int irq_detach(unsigned int irq) int irq_detach(unsigned int irq)
{ {
return irq_attach(irq, NULL); return irq_attach(irq, NULL);
} }
/* Interrupt Service Routine. */
void isr(void) void isr(void)
{ {
unsigned int irqs = irq_pending() & irq_getmask(); unsigned int irqs = irq_pending() & irq_getmask();
while (irqs) while (irqs) {
{ const unsigned int irq = __builtin_ctz(irqs);
const unsigned int irq = __builtin_ctz(irqs); if ((irq < CONFIG_CPU_INTERRUPTS) && irq_table[irq].isr)
if ((irq < CONFIG_CPU_INTERRUPTS) && irq_table[irq].isr) irq_table[irq].isr();
irq_table[irq].isr(); else {
else { irq_setmask(irq_getmask() & ~(1 << irq));
irq_setmask(irq_getmask() & ~(1<<irq)); printf("\n*** disabled spurious irq %d ***\n", irq);
printf("\n*** disabled spurious irq %d ***\n", irq); }
} irqs &= irqs - 1; /* Clear this IRQ (the first bit set). */
irqs &= irqs - 1; // clear this irq (the first bit set) }
}
} }
#endif #endif
#else #else
#if defined(__microwatt__) #if defined(__microwatt__)
void isr(uint64_t vec){}; void isr(uint64_t vec) {};
#else #else
void isr(void){}; void isr(void) {};
#endif #endif
#endif #endif