Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

altera_quartus: fix clock domain name

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2013-03-26 23:05:46 +01:00
parent 3b19dfc412
commit 38e92eb92b
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
mibuild/altera_quartus.py
View file

@ -14,7 +14,7 @@ def _add_period_constraint(platform, clk, period):
class CRG_SE(SimpleCRG):
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
_add_period_constraint(platform, self.cd.clk, period)
_add_period_constraint(platform, self.cd_sys.clk, period)
def _format_constraint(c):
if isinstance(c, Pins):