altera_quartus: fix clock domain name

2013-03-26 23:05:46 +01:00 · 2013-03-26 23:05:46 +01:00 · 38e92eb92b
parent 3b19dfc412
commit 38e92eb92b
1 changed files with 1 additions and 1 deletions
--- a/mibuild/altera_quartus.py
+++ b/mibuild/altera_quartus.py
@ -14,7 +14,7 @@ def _add_period_constraint(platform, clk, period):
 class CRG_SE(SimpleCRG):
 	def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
 		SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
-		_add_period_constraint(platform, self.cd.clk, period)
+		_add_period_constraint(platform, self.cd_sys.clk, period)

 def _format_constraint(c):
 	if isinstance(c, Pins):