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axi/axi_full: size/lock width are different on AXI3 and AXI4.

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Florent Kermarrec 2022-11-04 12:35:09 +01:00
parent 8f459a27dd
commit 38ee44a85a
1 changed files with 5 additions and 3 deletions
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8
litex/soc/interconnect/axi/axi_full.py
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@ -20,14 +20,16 @@ from litex.soc.interconnect.axi.axi_stream import AXIStreamInterface
# AXI Definition ----------------------------------------------------------------------------------- # AXI Definition -----------------------------------------------------------------------------------
def ax_description(address_width, version="axi4"): def ax_description(address_width, version="axi4"):
len_width = {"axi3":4, "axi4":8}[version] len_width = {"axi3":4, "axi4":8}[version]
size_width = {"axi3":4, "axi4":3}[version]
lock_width = {"axi3":2, "axi4":1}[version]
# * present for interconnect with others cores but not used by LiteX. # * present for interconnect with others cores but not used by LiteX.
return [ return [
("addr", address_width), # Address Width. ("addr", address_width), # Address Width.
("burst", 2), # Burst type. ("burst", 2), # Burst type.
("len", len_width), # Number of data (-1) transfers (up to 16 (AXI3) or 256 (AXI4)). ("len", len_width), # Number of data (-1) transfers (up to 16 (AXI3) or 256 (AXI4)).
("size", 4), # Number of bytes (-1) of each data transfer (up to 1024 bits). ("size", size_width), # Number of bytes (-1) of each data transfer (up to 1024-bit).
("lock", 2), # * ("lock", lock_width), # *
("prot", 3), # * ("prot", 3), # *
("cache", 4), # * ("cache", 4), # *
("qos", 4), # * ("qos", 4), # *