soc: add csr_regions, update copyright
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d2b069516a
commit
39011593ac
litex/soc/integration
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@ -70,11 +70,3 @@ def get_mem_data(filename_or_regions, endianness="big", mem_size=None):
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data[int(base, 16)//4 + i] = struct.unpack(">I", w)[0]
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i += 1
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return data
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# SoC primitives -----------------------------------------------------------------------------------
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class SoCCSRRegion:
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def __init__(self, origin, busword, obj):
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self.origin = origin
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self.busword = busword
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self.obj = obj
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@ -1,4 +1,5 @@
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# License: BSD
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import logging
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@ -20,6 +21,7 @@ from litex.soc.interconnect import wishbone2csr
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# - replace raise with exit on logging error.
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# - add configurable CSR paging.
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# - manage SoCLinkerRegion
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# - cleanup SoCCSRRegion
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logging.basicConfig(level=logging.INFO)
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@ -81,6 +83,14 @@ class SoCIORegion(SoCRegion): pass
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class SoCLinkerRegion(SoCRegion): pass
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# SoCCSRRegion -------------------------------------------------------------------------------------
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class SoCCSRRegion:
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def __init__(self, origin, busword, obj):
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self.origin = origin
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self.busword = busword
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self.obj = obj
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# SoCBusHandler ------------------------------------------------------------------------------------
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class SoCBusHandler(Module):
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@ -476,6 +486,7 @@ class SoCCSRHandler(SoCLocHandler):
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self.alignment = alignment
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self.paging = paging
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self.masters = {}
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self.regions = {}
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self.logger.info("{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
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colorer(self.data_width),
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colorer(2**self.address_width/2**10),
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@ -509,6 +520,11 @@ class SoCCSRHandler(SoCLocHandler):
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colorer(name, color="underline"),
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colorer("added", color="green")))
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# Add Region -----------------------------------------------------------------------------------
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def add_region(self, name, region):
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# FIXME: add checks
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self.regions[name] = region
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# Address map ----------------------------------------------------------------------------------
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def address_map(self, name, memory):
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if memory is not None:
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@ -625,6 +641,7 @@ class SoC(Module):
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self.platform = platform
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self.sys_clk_freq = sys_clk_freq
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self.constants = {}
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self.csr_regions = {}
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# SoC Bus Handler --------------------------------------------------------------------------
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self.submodules.bus = SoCBusHandler(
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@ -816,6 +833,27 @@ class SoC(Module):
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masters = list(self.csr.masters.values()),
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slaves = self.csr_bankarray.get_buses())
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# Add CSRs regions
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for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
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self.csr.add_region(name, SoCCSRRegion(
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origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
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busword = self.csr.data_width,
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obj = csrs))
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# Add Memory regions
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for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
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self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion(
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origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
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busworkd = self.csr.data_width,
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obj = memory))
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# Sort CSR regions by origin
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self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)}
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# Add CSRs / Config items to constants
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for name, constant in self.csr_bankarray.constants:
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self.add_constant(name + "_" + constant.name, constant.value.value)
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# SoC CPU Check ----------------------------------------------------------------------------
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if not isinstance(self.cpu, cpu.CPUNone):
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for name in ["rom", "sram"]:
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@ -92,7 +92,6 @@ class SoCCore(SoC):
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# SoC's Config/Constants/Regions
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self.config = {}
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self.csr_regions = {}
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# Parameters managment ---------------------------------------------------------------------
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if cpu_type == "None":
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@ -197,30 +196,12 @@ class SoCCore(SoC):
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# Finalization ---------------------------------------------------------------------------------
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def do_finalize(self):
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# retro-compat
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SoC.do_finalize(self)
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# Retro-compatibility
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for region in self.bus.regions.values():
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region.length = region.size
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region.type = "cached" if region.cached else "io"
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SoC.do_finalize(self)
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# Add CSRs regions
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for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
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self.add_csr_region(name, (self.bus.regions["csr"].origin + 0x800*mapaddr),
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self.csr.data_width, csrs)
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# Add Memory regions
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for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
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self.add_csr_region(name + "_" + memory.name_override,
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(self.bus.regions["csr"].origin + 0x800*mapaddr),
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self.csr.data_width, memory)
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# Sort CSR regions by origin
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self.csr_regions = {k: v for k, v in sorted(self.csr_regions.items(), key=lambda item: item[1].origin)}
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# Add CSRs / Config items to constants
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for name, constant in self.csr_bankarray.constants:
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self.add_constant(name + "_" + constant.name, constant.value.value)
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self.csr_regions = self.csr.regions
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for name, value in self.config.items():
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self.add_config(name, value)
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