soc: add csr_regions, update copyright

litex/soc/integration/common.py

@@ -70,11 +70,3 @@ def get_mem_data(filename_or_regions, endianness="big", mem_size=None):
                     data[int(base, 16)//4 + i] = struct.unpack(">I", w)[0]
                 i += 1
     return data
-
-# SoC primitives -----------------------------------------------------------------------------------
-
-class SoCCSRRegion:
-    def __init__(self, origin, busword, obj):
-        self.origin  = origin
-        self.busword = busword
-        self.obj     = obj

litex/soc/integration/soc.py

@@ -1,4 +1,5 @@
-# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
 # License: BSD
 
 import logging
@@ -20,6 +21,7 @@ from litex.soc.interconnect import wishbone2csr
 # - replace raise with exit on logging error.
 # - add configurable CSR paging.
 # - manage SoCLinkerRegion
+# - cleanup SoCCSRRegion
 
 logging.basicConfig(level=logging.INFO)
 
@@ -81,6 +83,14 @@ class SoCIORegion(SoCRegion): pass
 
 class SoCLinkerRegion(SoCRegion): pass
 
+# SoCCSRRegion -------------------------------------------------------------------------------------
+
+class SoCCSRRegion:
+    def __init__(self, origin, busword, obj):
+        self.origin  = origin
+        self.busword = busword
+        self.obj     = obj
+
 # SoCBusHandler ------------------------------------------------------------------------------------
 
 class SoCBusHandler(Module):
@@ -476,6 +486,7 @@ class SoCCSRHandler(SoCLocHandler):
         self.alignment     = alignment
         self.paging        = paging
         self.masters       = {}
+        self.regions       = {}
         self.logger.info("{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
             colorer(self.data_width),
             colorer(2**self.address_width/2**10),
@@ -509,6 +520,11 @@ class SoCCSRHandler(SoCLocHandler):
             colorer(name,    color="underline"),
             colorer("added", color="green")))
 
+    # Add Region -----------------------------------------------------------------------------------
+    def add_region(self, name, region):
+        # FIXME: add checks
+        self.regions[name] = region
+
     # Address map ----------------------------------------------------------------------------------
     def address_map(self, name, memory):
         if memory is not None:
@@ -625,6 +641,7 @@ class SoC(Module):
         self.platform     = platform
         self.sys_clk_freq = sys_clk_freq
         self.constants    = {}
+        self.csr_regions  = {}
 
         # SoC Bus Handler --------------------------------------------------------------------------
         self.submodules.bus = SoCBusHandler(
@@ -816,6 +833,27 @@ class SoC(Module):
                 masters = list(self.csr.masters.values()),
                 slaves  = self.csr_bankarray.get_buses())
 
+        # Add CSRs regions
+        for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
+            self.csr.add_region(name, SoCCSRRegion(
+                origin   = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
+                busword  = self.csr.data_width,
+                obj      = csrs))
+
+        # Add Memory regions
+        for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
+            self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion(
+                origin   = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
+                busworkd = self.csr.data_width,
+                obj      = memory))
+
+        # Sort CSR regions by origin
+        self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)}
+
+        # Add CSRs / Config items to constants
+        for name, constant in self.csr_bankarray.constants:
+            self.add_constant(name + "_" + constant.name, constant.value.value)
+
         # SoC CPU Check ----------------------------------------------------------------------------
         if not isinstance(self.cpu, cpu.CPUNone):
             for name in ["rom", "sram"]:

litex/soc/integration/soc_core.py

@@ -92,7 +92,6 @@ class SoCCore(SoC):
 
         # SoC's Config/Constants/Regions
         self.config      = {}
-        self.csr_regions = {}
 
         # Parameters managment ---------------------------------------------------------------------
         if cpu_type == "None":
@@ -197,30 +196,12 @@ class SoCCore(SoC):
     # Finalization ---------------------------------------------------------------------------------
 
     def do_finalize(self):
-        # retro-compat
+        SoC.do_finalize(self)
+        # Retro-compatibility
         for region in self.bus.regions.values():
             region.length = region.size
             region.type   = "cached" if region.cached else "io"
-
+        self.csr_regions = self.csr.regions
-        SoC.do_finalize(self)
-
-        # Add CSRs regions
-        for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
-            self.add_csr_region(name, (self.bus.regions["csr"].origin + 0x800*mapaddr),
-                self.csr.data_width, csrs)
-
-        # Add Memory regions
-        for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
-            self.add_csr_region(name + "_" + memory.name_override,
-                (self.bus.regions["csr"].origin + 0x800*mapaddr),
-                self.csr.data_width, memory)
-
-        # Sort CSR regions by origin
-        self.csr_regions = {k: v for k, v in sorted(self.csr_regions.items(), key=lambda item: item[1].origin)}
-
-        # Add CSRs / Config items to constants
-        for name, constant in self.csr_bankarray.constants:
-            self.add_constant(name + "_" + constant.name, constant.value.value)
         for name, value in self.config.items():
             self.add_config(name, value)