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soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined

This commit is contained in:
Florent Kermarrec 2020-02-06 19:50:44 +01:00
parent 1eff0799a4
commit 39458c92eb
2 changed files with 27 additions and 24 deletions
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5
litex/soc/integration/soc.py
View File

@ -404,8 +404,9 @@ class SoCIRQ:
self.logger.info(colorer("IRQ Handler created.", color="cyan")) self.logger.info(colorer("IRQ Handler created.", color="cyan"))
# Add ------------------------------------------------------------------------------------------ # Add ------------------------------------------------------------------------------------------
def add(self, name, n=None): def add(self, name, n=None, use_loc_if_exists=False):
allocated = False allocated = False
if not (use_loc_if_exists and name in self.irqs.keys()):
if name in self.irqs.keys(): if name in self.irqs.keys():
self.logger.error("{} IRQ name already used.".format(colorer(name, "red"))) self.logger.error("{} IRQ name already used.".format(colorer(name, "red")))
self.logger.error(self) self.logger.error(self)
@ -427,6 +428,8 @@ class SoCIRQ:
colorer(n, color="red"), colorer(n, color="red"),
colorer(self.n_csrs, color="green"))) colorer(self.n_csrs, color="green")))
raise raise
else:
n = self.irqs[name]
self.irqs[name] = n self.irqs[name] = n
self.logger.info("{} IRQ {} at Location {}.".format( self.logger.info("{} IRQ {} at Location {}.".format(
colorer(name, color="underline"), colorer(name, color="underline"),

6
litex/soc/integration/soc_core.py
View File

@ -265,7 +265,7 @@ class SoCCore(SoC):
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy)) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True) self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True) self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart") self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier # Add Identifier
if ident: if ident:
@ -279,7 +279,7 @@ class SoCCore(SoC):
if with_timer: if with_timer:
self.submodules.timer0 = timer.Timer() self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True) self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0") self.add_interrupt("timer0", allow_user_defined=True)
# Add Wishbone to CSR bridge # Add Wishbone to CSR bridge
self.config["CSR_DATA_WIDTH"] = csr_data_width self.config["CSR_DATA_WIDTH"] = csr_data_width
@ -298,7 +298,7 @@ class SoCCore(SoC):
# Methods -------------------------------------------------------------------------------------- # Methods --------------------------------------------------------------------------------------
def add_interrupt(self, interrupt_name, interrupt_id=None, allow_user_defined=False): def add_interrupt(self, interrupt_name, interrupt_id=None, allow_user_defined=False):
self.irq.add(interrupt_name, interrupt_id) self.irq.add(interrupt_name, interrupt_id, use_loc_if_exists=allow_user_defined)
def add_csr(self, csr_name, csr_id=None, allow_user_defined=False): def add_csr(self, csr_name, csr_id=None, allow_user_defined=False):
self.csr.add(csr_name, csr_id, use_loc_if_exists=allow_user_defined) self.csr.add(csr_name, csr_id, use_loc_if_exists=allow_user_defined)