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interconnect/wishbone/DownConverter: skip accesses on slave when sel==0 and simplify. 

Improve efficiency for 64-bit CPU accessing only the 32-bit LSBs/MSBs.
This commit is contained in:
Florent Kermarrec 2020-06-01 11:03:08 +02:00
parent 511832a911
commit 395af900fd
1 changed files with 10 additions and 31 deletions
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41
litex/soc/interconnect/wishbone.py
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@ -245,34 +245,19 @@ class DownConverter(Module):
fsm.act("IDLE", fsm.act("IDLE",
NextValue(counter, 0), NextValue(counter, 0),
If(master.stb & master.cyc, If(master.stb & master.cyc,
If(master.we, NextState("CONVERT"),
NextState("WRITE")
).Else(
NextState("READ")
)
) )
) )
fsm.act("WRITE", fsm.act("CONVERT",
slave.adr.eq(Cat(counter, master.adr)), slave.adr.eq(Cat(counter, master.adr)),
slave.we.eq(1), Case(counter, {i: slave.sel.eq(master.sel[i*dw_to//8:]) for i in range(ratio)}),
slave.cyc.eq(1),
If(master.stb & master.cyc, If(master.stb & master.cyc,
slave.stb.eq(1), If(slave.sel != 0,
If(slave.ack, slave.we.eq(master.we),
NextValue(counter, counter + 1), slave.cyc.eq(1),
If(counter == (ratio - 1), slave.stb.eq(1),
master.ack.eq(1), ),
NextState("IDLE") If(slave.ack | (slave.sel == 0),
)
)
)
)
fsm.act("READ",
slave.adr.eq(Cat(counter, master.adr)),
slave.cyc.eq(1),
If(master.stb & master.cyc,
slave.stb.eq(1),
If(slave.ack,
NextValue(counter, counter + 1), NextValue(counter, counter + 1),
If(counter == (ratio - 1), If(counter == (ratio - 1),
master.ack.eq(1), master.ack.eq(1),
@ -283,13 +268,7 @@ class DownConverter(Module):
) )
# Write Datapath # Write Datapath
cases = {} self.comb += Case(counter, {i: slave.dat_w.eq(master.dat_w[i*dw_to:]) for i in range(ratio)})
for i in range(ratio):
cases[i] = [
slave.sel.eq(master.sel[i*dw_to//8:]),
slave.dat_w.eq(master.dat_w[i*dw_to:]),
]
self.comb += Case(counter, cases)
# Read Datapath # Read Datapath
dat_r = Signal(dw_from, reset_less=True) dat_r = Signal(dw_from, reset_less=True)