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Remove ActorNode

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This commit is contained in:
Sebastien Bourdeauducq 2012-12-12 22:52:55 +01:00
parent 053f8ed82c
commit 3986790621
1 changed files with 16 additions and 16 deletions
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32
milkymist/framebuffer/__init__.py
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@ -172,18 +172,18 @@ class Framebuffer:
pack_factor = asmiport.hub.dw//_bpp pack_factor = asmiport.hub.dw//_bpp
packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor) packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits)) fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits)) adrloop = misc.IntSequence(length_bits, asmi_bits)
adrbuffer = ActorNode(plumbing.Buffer) adrbuffer = AbstractActor(plumbing.Buffer)
dma = ActorNode(dma_asmi.Reader(asmiport)) dma = dma_asmi.Reader(asmiport)
datbuffer = ActorNode(plumbing.Buffer) datbuffer = AbstractActor(plumbing.Buffer)
cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels)) cast = structuring.Cast(asmiport.hub.dw, packed_pixels)
unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout)) unpack = structuring.Unpack(pack_factor, _pixel_layout)
vtg = ActorNode(VTG()) vtg = VTG()
if simulation: if simulation:
fifo = ActorNode(sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout))) fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout))
else: else:
fifo = ActorNode(FIFO()) fifo = FIFO()
g = DataFlowGraph() g = DataFlowGraph()
g.add_connection(fi, adrloop, source_subr=["length", "base"]) g.add_connection(fi, adrloop, source_subr=["length", "base"])
@ -199,20 +199,20 @@ class Framebuffer:
g.add_connection(vtg, fifo) g.add_connection(vtg, fifo)
self._comp_actor = CompositeActor(g, debugger=False) self._comp_actor = CompositeActor(g, debugger=False)
self.bank = csrgen.Bank(fi.actor.get_registers() + self._comp_actor.get_registers(), self.bank = csrgen.Bank(fi.get_registers() + self._comp_actor.get_registers(),
address=address) address=address)
# Pads # Pads
self.vga_psave_n = Signal() self.vga_psave_n = Signal()
if not simulation: if not simulation:
self.vga_hsync_n = fifo.actor.vga_hsync_n self.vga_hsync_n = fifo.vga_hsync_n
self.vga_vsync_n = fifo.actor.vga_vsync_n self.vga_vsync_n = fifo.vga_vsync_n
self.vga_sync_n = Signal() self.vga_sync_n = Signal()
self.vga_blank_n = Signal() self.vga_blank_n = Signal()
if not simulation: if not simulation:
self.vga_r = fifo.actor.vga_r self.vga_r = fifo.vga_r
self.vga_g = fifo.actor.vga_g self.vga_g = fifo.vga_g
self.vga_b = fifo.actor.vga_b self.vga_b = fifo.vga_b
def get_fragment(self): def get_fragment(self):
comb = [ comb = [