Standardize the `cpu_variant` strings.
Current valid `cpu_variant` values; * minimal (alias: min) * lite (alias: light, zephyr, nuttx) * standard (alias: std) - Default * full (alias: everything) * linux Fully documented in the [docs/Soft-CPU.md](docs/Soft-CPU.md) file mirrored from the [LiteX-BuildEnv Wiki](https://github.com/timvideos/litex-buildenv/wiki). Also support "extensions" which are added to the `cpu_variant` with a `+`. Currently only the `debug` extension is supported. In future hope to add `mmu` and `hmul` extensions.
This commit is contained in:
Tim 'mithro' Ansell
parent
e42de8fe52
commit
39c579baa2
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@ -12,8 +12,8 @@ class LM32(Module):
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gcc_flags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled"
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linker_output_format = "elf32-lm32"
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def __init__(self, platform, eba_reset, variant=None):
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assert variant in (None, "lite", "minimal"), "Unsupported variant %s" % variant
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def __init__(self, platform, eba_reset, variant="standard"):
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assert variant in ("standard", "lite", "minimal"), "Unsupported variant %s" % variant
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self.reset = Signal()
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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@ -66,7 +66,7 @@ class LM32(Module):
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self.add_sources(platform, variant)
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@staticmethod
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def add_sources(platform, variant=None):
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def add_sources(platform, variant):
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vdir = os.path.join(
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os.path.abspath(os.path.dirname(__file__)), "verilog")
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platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
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@ -93,5 +93,7 @@ class LM32(Module):
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platform.add_verilog_include_path(os.path.join(vdir, "config_minimal"))
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elif variant == "lite":
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platform.add_verilog_include_path(os.path.join(vdir, "config_lite"))
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else:
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elif variant == "standard":
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platform.add_verilog_include_path(os.path.join(vdir, "config"))
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else:
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raise TypeError("Unknown variant {}".format(variant))
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@ -12,8 +12,8 @@ class Minerva(Module):
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gcc_flags = "-D__minerva__ -march=rv32i -mabi=ilp32"
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linker_output_format = "elf32-littleriscv"
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def __init__(self, platform, cpu_reset_address, variant=None):
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assert variant is None, "Unsupported variant %s" % variant
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def __init__(self, platform, cpu_reset_address, variant="standard"):
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assert variant is "standard", "Unsupported variant %s" % variant
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self.reset = Signal()
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self.ibus = wishbone.Interface()
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self.dbus = wishbone.Interface()
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@ -1,3 +1,4 @@
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#!/usr/bin/env python3
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import os
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from migen import *
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@ -12,8 +13,8 @@ class MOR1KX(Module):
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gcc_flags = "-mhard-mul -mhard-div -mror"
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linker_output_format = "elf32-or1k"
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def __init__(self, platform, reset_pc, variant=None):
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assert variant in (None, "linux"), "Unsupported variant %s" % variant
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def __init__(self, platform, reset_pc, variant="standard"):
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assert variant in ("standard", "linux"), "Unsupported variant %s" % variant
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self.reset = Signal()
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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@ -47,7 +48,7 @@ class MOR1KX(Module):
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p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
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)
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if variant == None:
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if variant == "standard":
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# Use the default configuration
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pass
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elif variant == "linux":
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@ -1,3 +1,4 @@
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#!/usr/bin/env python3
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import os
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from migen import *
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@ -12,7 +13,7 @@ class PicoRV32(Module):
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gcc_flags_template = "-D__picorv32__ -mno-save-restore -march=rv32{ext} -mabi=ilp32"
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linker_output_format = "elf32-littleriscv"
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def __init__(self, platform, progaddr_reset, variant):
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def __init__(self, platform, progaddr_reset, variant="standard"):
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self.gcc_flags = ""
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self.reset = Signal()
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@ -61,7 +62,7 @@ class PicoRV32(Module):
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"p_STACKADDR" : 0xffffffff
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}
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if variant == None:
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if variant == "standard":
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self.gcc_flags = PicoRV32.gcc_flags_template.format(ext="im")
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elif variant == "minimal":
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picorv32_params.update({
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@ -6,18 +6,51 @@ from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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CPU_VARIANTS = {
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"minimal": "VexRiscv_Min",
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"minimal+debug": "VexRiscv_MinDebug",
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"lite": "VexRiscv_Lite",
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"lite+debug": "VexRiscv_LiteDebug",
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"standard": "VexRiscv",
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"standard+debug": "VexRiscv_Debug",
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"full": "VexRiscv_Full",
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"full+debug": "VexRiscv_FullDebug",
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"linux": "VexRiscv_Linux",
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}
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GCC_FLAGS = {
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# /-------- Base ISA
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# |/------- Hardware Multiply + Divide
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# ||/----- Atomics
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# |||/---- Compressed ISA
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# ||||/--- Single-Precision Floating-Point
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# |||||/-- Double-Precision Floating-Point
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# imacfd
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"minimal": "-march=rv32i -mabi=ilp32",
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"minimal+debug": "-march=rv32i -mabi=ilp32",
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"lite": "-march=rv32i -mabi=ilp32",
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"lite+debug": "-march=rv32i -mabi=ilp32",
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"standard": "-march=rv32im -mabi=ilp32",
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"standard+debug": "-march=rv32im -mabi=ilp32",
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# Does full have floating point? - Add -march=fd, and -mabi=fd
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"full": "-march=rv32imac -mabi=ilp32",
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"full+debug": "-march=rv32imac -mabi=ilp32",
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"linux": "-march=rv32imac -mabi=ilp32",
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}
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class VexRiscv(Module, AutoCSR):
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name = "vexriscv"
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endianness = "little"
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gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf")
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gcc_flags = "-D__vexriscv__ -march=rv32im -mabi=ilp32"
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linker_output_format = "elf32-littleriscv"
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def __init__(self, platform, cpu_reset_address, variant=None):
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variant = "std" if variant is None else variant
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variant = "std_debug" if variant == "debug" else variant
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variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug", "full", "full_debug")
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assert variant in variants, "Unsupported variant %s" % variant
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def __init__(self, platform, cpu_reset_address, variant="standard"):
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assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
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self.gcc_flags = GCC_FLAGS[variant]
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self.platform = platform
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self.variant = variant
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self.external_variant = None
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@ -150,18 +183,8 @@ class VexRiscv(Module, AutoCSR):
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)
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@staticmethod
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def add_sources(platform, variant="std"):
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verilog_variants = {
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"std": "VexRiscv.v",
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"std_debug": "VexRiscv_Debug.v",
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"lite": "VexRiscv_Lite.v",
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"lite_debug": "VexRiscv_LiteDebug.v",
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"min": "VexRiscv_Min.v",
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"min_debug": "VexRiscv_MinDebug.v",
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"full": "VexRiscv_Full.v",
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"full_debug": "VexRiscv_FullDebug.v",
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}
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cpu_filename = verilog_variants[variant]
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def add_sources(platform, variant="standard"):
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cpu_filename = CPU_VARIANTS[variant]
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vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
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platform.add_source(os.path.join(vdir, cpu_filename))
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@ -1,3 +1,4 @@
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#!/usr/bin/env python3
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import os
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import struct
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import inspect
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@ -23,6 +24,42 @@ __all__ = [
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]
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CPU_VARIANTS = {
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# "official name": ["alias 1", "alias 2"],
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"minimal" : ["min",],
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"lite" : ["light", "zephyr", "nuttx"],
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"standard": [None, "std"],
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"full": [],
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"linux" : [],
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}
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CPU_VARIANTS_EXTENSIONS = ["debug"]
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class InvalidCPUVariantError(ValueError):
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def __init__(self, variant):
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msg = """\
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Invalid cpu_variant value: {}
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Possible Values:
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""".format(variant)
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for k, v in CPU_VARIANTS.items():
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msg += " - {} (aliases: {})\n".format(k, ", ".join(str(s) for s in v))
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ValueError.__init__(self, msg)
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class InvalidCPUExtensionError(ValueError):
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def __init__(self, variant):
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msg = """\
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Invalid extension in cpu_variant value: {}
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Possible Values:
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""".format(variant)
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for e in CPU_VARIANTS_EXTENSIONS.items():
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msg += " - {}\n".format(e)
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ValueError.__init__(self, msg)
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def version(with_time=True):
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import datetime
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import time
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@ -77,6 +114,7 @@ def get_mem_data(filename, endianness="big", mem_size=None):
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i += 1
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return data
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class ReadOnlyDict(dict):
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def __readonly__(self, *args, **kwargs):
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raise RuntimeError("Cannot modify ReadOnlyDict")
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@ -162,7 +200,25 @@ class SoCCore(Module):
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if cpu_type == "None":
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cpu_type = None
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self.cpu_type = cpu_type
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self.cpu_variant = cpu_variant
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# Support the old style which used underscore for separator
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cpu_variant = cpu_variant.replace('_', '+')
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# Check for valid CPU variants.
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cpu_variant_processor, *cpu_variant_ext = cpu_variant.split('+')
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for key, values in CPU_VARIANTS.items():
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if cpu_variant_processor not in [key,]+values:
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continue
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self.cpu_variant = key
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break
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else:
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raise InvalidCPUVariantError(cpu_variant)
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# Check for valid CPU extensions.
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for ext in sorted(cpu_variant_ext):
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if cpu_variant_ext not in CPU_VARIANTS_EXTENSIONS:
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raise InvalidCPUExtension(cpu_variant)
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self.cpu_variant += "+"+ext
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if integrated_rom_size:
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cpu_reset_address = self.mem_map["rom"]
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self.cpu_reset_address = cpu_reset_address
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